refactor(qemu): common BL31 sources

Move BL31 source list into common file.

Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not

refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.

Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie

refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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fix(nuvoton): fix typo in platform.mk

Fix typo of SPMD_SPM_AT_SEL2 in platform.mk

Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: I06cfe2f1f0783edff513d83fef08eeed5f4fc58b

fix(scmi): add parameter for plat_scmi_clock_rates_array

Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.

Signed-off-by: XiaoDong

fix(scmi): add parameter for plat_scmi_clock_rates_array

Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I97c6751e7d34c839ced8f22bddc39fb534978cc4

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Merge "build(juno): added error check for BL32 dependency" into integration

Merge "feat(fdts/morello): add thermal framework" into integration

Merge "fix(versal-net): don't clear pending interrupts" into integration

Merge "fix(zynqmp): validate clock_id to avoid OOB variable access" into integration

build(juno): added error check for BL32 dependency

Macro PLAT_ARM_MAX_BL32_SIZE definition is dependent on
JUNO_AARCH32_EL3_RUNTIME=1. When this value is not set and building
for AArch32, the build

build(juno): added error check for BL32 dependency

Macro PLAT_ARM_MAX_BL32_SIZE definition is dependent on
JUNO_AARCH32_EL3_RUNTIME=1. When this value is not set and building
for AArch32, the build fails as it cannot find the definition of the
first macro. With this patch, the problem is addressed by producing
an error when the dependency is not set properly.

Change-Id: Ibe4e976bf79892fd26f3b266bd546218f5616825
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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fix(versal-net): don't clear pending interrupts

All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.

Signed-of

fix(versal-net): don't clear pending interrupts

All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f

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fix(zynqmp): validate clock_id to avoid OOB variable access

The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
ac

fix(zynqmp): validate clock_id to avoid OOB variable access

The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
access for ext_clocks variable.

Add check in the pm_api_clock_get_name() to validate clock_id against
CLK_MAX.

Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: Ifa0033d2c557efd6a87b40e366560bc3ba8c602b

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Merge "refactor(cm): move remaining EL2 save/restore into C" into integration

refactor(cm): move remaining EL2 save/restore into C

MTE and common system registers are the last remaining EL2 save/restores
in assembly. Convert them to C, like all the others.

Signed-off-by: Boy

refactor(cm): move remaining EL2 save/restore into C

MTE and common system registers are the last remaining EL2 save/restores
in assembly. Convert them to C, like all the others.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If690f792e70b97fd4b4cd5f43847a71719b128f1

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Merge "refactor(cpufeat): introduce wrapper macro for read_feat_...() functions" into integration

refactor(cpufeat): introduce wrapper macro for read_feat_...() functions

At the moment we have some elaborate, but very schematic functions to
allow checking for CPU feature enablement. Adding some

refactor(cpufeat): introduce wrapper macro for read_feat_...() functions

At the moment we have some elaborate, but very schematic functions to
allow checking for CPU feature enablement. Adding some more becomes
tedious and is also error-prone.

Provide two wrapper macros that reduce most of the features to a
single line:
- CREATE_FEATURE_FUNCS(name, idreg, idfield, guard)
creates two functions read_<name>_id_field() and is_<name>_supported(),
that check the 4-bit CPU ID field starting at bit <idfield> in <idreg>
for being not 0, and compares it against the build time <guard> symbol.
For the usual feature (like PAN) this looks like:
CREATE_FEATURE_FUNCS(feat_pan, id_aa64mmfr1_el1,
ID_AA64MMFR1_EL1_PAN_SHIFT, ENABLE_FEAT_PAN)

- CREATE_FEATURE_FUNCS_VER(name, read_func, idvalue, guard)
creates one function to check for a certain CPU ID field *value*, so
when "!= 0" is not sufficient. It's meant to be used in addition to
the above macro, since that generates the CPU ID field accessor
function:
CREATE_FEATURE_FUNCS(feat_amu, id_aa64pfr0_el1, ID_AA64PFR0_AMU_SHIFT,
ENABLE_FEAT_AMU)
CREATE_FEATURE_FUNCS_VER(feat_amuv1p1, read_feat_amu_id_field,
ID_AA64PFR0_AMU_V1P1, ENABLE_FEAT_AMUv1p1)

Describe the existing feature accessor functions using those new macros,
to reduce the size of the file, improve readability and decrease the
possibility of (copy&paste) bugs.

Change-Id: Ib136a875b4857058ff561c4635ace344006f29bf
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "docs(psa): doc AP/RSS interfaces for NV ctrs/ROTPK" into integration

feat(fdts/morello): add thermal framework

Add thermal zones, cooling maps (passive cooling via DVFS),
trip points, etc. for Morello SoC.

Change-Id: I5bbc2999a5fd16ebbb3bb2f987eeb42f70961b98
Signed-

feat(fdts/morello): add thermal framework

Add thermal zones, cooling maps (passive cooling via DVFS),
trip points, etc. for Morello SoC.

Change-Id: I5bbc2999a5fd16ebbb3bb2f987eeb42f70961b98
Signed-off-by: Anurag Koul <anurag.koul@arm.com>

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feat(ethos-n): update npu error handling

Changes have been made in NPU firmware version 13 around error handling
which require some different register values to be set in AUXCTLR and
SYSCTRL1.

SiP

feat(ethos-n): update npu error handling

Changes have been made in NPU firmware version 13 around error handling
which require some different register values to be set in AUXCTLR and
SYSCTRL1.

SiP service version number has been bumped up to 15 to reflect these
changes.

Change-Id: I6cda0048dc75df2150f7a0fe25f12ba6bf119ced
Signed-off-by: Rob Hughes <robert.hughes@arm.com>

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Merge "feat(cpus): add support for Gelas CPU" into integration

Merge changes from topic "el3_direct_msg" into integration

* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition

Merge changes from topic "el3_direct_msg" into integration

* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
feat(spmd): get logical partitions info
feat(spmd): add partition info get regs
refactor(ff-a): move structure definitions
feat(spmd): el3 direct message API
feat(spmd): add spmd logical partitions

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feat(mt8188): add support for SMC from OP-TEE

- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE.
- Register optee for EMI MPU.

Change-Id: Ie94542f0e3966c4c25f2b7233b9355d41f8f36

feat(mt8188): add support for SMC from OP-TEE

- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE.
- Register optee for EMI MPU.

Change-Id: Ie94542f0e3966c4c25f2b7233b9355d41f8f36a5
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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Merge "feat(sptool): generate `ARM_BL2_SP_LIST_DTS` file from `sp_layout.json`" into integration

docs(spm): document new build option

Add documentation for the new build option ENABLE_SPMD_LP.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I808e6c00e3699fc900dc97e889af

docs(spm): document new build option

Add documentation for the new build option ENABLE_SPMD_LP.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I808e6c00e3699fc900dc97e889af63cc01cae794

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