Merge changes from topic "sm_bk/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata fr

Merge changes from topic "sm_bk/errata_refactor" into integration

* changes:
refactor(cpus): convert the Cortex-A57 to use cpu helpers
refactor(cpus): convert the Cortex-A57 to use the errata framework
refactor(cpus): reorder Cortex-A57 errata by ascending order
refactor(cpus): add Cortex-A57 errata framework information
refactor(cpus): convert the Cortex-A53 to use cpu helpers
refactor(cpus): convert the Cortex-A53 to use the errata framework
refactor(cpus): reorder Cortex-A53 errata by ascending order

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Merge "fix(nuvoton): fix typo in platform.mk" into integration

fix(ufs): set data segment length

Remove blanket assumption of empty data segment area to avoid
issues while writing descriptors.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: If6ff0426

fix(ufs): set data segment length

Remove blanket assumption of empty data segment area to avoid
issues while writing descriptors.

Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: If6ff0426c44c949af1065082ed8a23ed936b5f3e

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Merge "build(bl32): added check for AARCH32_SP" into integration

Merge "fix(cpus): check for SME presence in Gelas" into integration

refactor(cpus): convert the Cortex-A57 to use cpu helpers

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1cc10fa91cb9c837386144249dafeb6178d5866e

refactor(cpus): convert the Cortex-A57 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp

refactor(cpus): convert the Cortex-A57 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.

At this point the binary output of all errata was checked with the
script from commit 19136. All reported discrepancies involve errata
with no workaround in the cpu file or errata that did not previously
have a workaround function and now do. The non temporal hint erratum has
been converted to a numeric erratum.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib321ab01362c5954fe78e7349229c1437b3da847

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refactor(cpus): reorder Cortex-A57 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition

refactor(cpus): reorder Cortex-A57 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ia98976797fc0811f30c7dbf714e94b36e3c2263e

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refactor(cpus): add Cortex-A57 errata framework information

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic435b8d42639454fabb587ead44f646f7285cc40

refactor(cpus): convert the Cortex-A53 to use cpu helpers

Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.

Alt

refactor(cpus): convert the Cortex-A53 to use cpu helpers

Also, convert checker functions of errata which are enabled for all cpu
revisions to report correctly in preparation of the errata ABI.

Although the script from commit 250919 was used to check that errata
code did not change, this CPU only loosely adhered to convention and its
output was not particularly useful. Nevertheless, the discrepancies were
manually verified. All errata have been checked that they get invoked.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I988db6e7b6d1732f1d2258dbdf945cb475781894

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refactor(cpus): convert the Cortex-A53 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cp

refactor(cpus): convert the Cortex-A53 to use the errata framework

This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive

It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I30556f438859d17f054cb6bc96f3069b40474b58

show more ...

refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition

refactor(cpus): reorder Cortex-A53 errata by ascending order

Errata report order is enforced to be in ascending order. To achieve
this with the errata framework this has to be done at the definition
level.

Also rename the disable_non_temporal_hint to its erratum number to
conform to convention.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Id474872afebf361ab3d21c454ab3624db8354045

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fix(cpus): check for SME presence in Gelas

The original powerdown function for Gelas included SME disabling
instructions but did not check for the presence of SME before disabling.
This could lead t

fix(cpus): check for SME presence in Gelas

The original powerdown function for Gelas included SME disabling
instructions but did not check for the presence of SME before disabling.
This could lead to unexpected beaviors. This patch adds that check so
the feature is disabled only if it is present.

Change-Id: I582db53a6669317620e4f72a3eac87525897d3d0
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the

build(bl32): added check for AARCH32_SP

If AACRH32_SP is not specified, it causes the DEFAULT_LINKER_SCRIPT
variable to be empty, and then the linker takes the variable following
it as if it was the linker script, which is not one. This patch
addresses that issue by requiring the AARCH32_SP variable to be set
before continuing.

Change-Id: I21db7d5bd86b98faaa1a1cd3f985daa592556a2d
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge "feat(mt8188): add support for SMC from OP-TEE" into integration

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xf

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response")
Change-Id: I03a808fa0bf2cbefbc1c9924bdaf4cfb2ad7f2cb
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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Merge "refactor(qemu): handle pointer authentication" into integration

refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszki

refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge changes from topic "unify-qemu-machines" into integration

* changes:
refactor(qemu): move options to start of file
refactor(qemu): keep AArch64 cpu flags in one section

Merge changes from topic "unify-qemu-machines" into integration

* changes:
refactor(qemu): handle SPM_MM builds
refactor(qemu): handle AArch64 flags
refactor(qemu): common cpu features enablem

Merge changes from topic "unify-qemu-machines" into integration

* changes:
refactor(qemu): handle SPM_MM builds
refactor(qemu): handle AArch64 flags
refactor(qemu): common cpu features enablement
refactor(qemu): common BL31 sources
refactor(qemu): common BL1/2 sources
refactor(qemu): move CPU definitions into one place
refactor(qemu): move FDT stuff into one place

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refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: M

refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c85

refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14

refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24

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refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar

refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <ma

refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a

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