fix(xlat): set MAX_PHYS_ADDR to total mapped physical region

Currently some platforms set PLAT_XLAT_TABLES_DYNAMIC=0 and
define it unconditionally also in platform Makefiles.
Due to this when PLAT_X

fix(xlat): set MAX_PHYS_ADDR to total mapped physical region

Currently some platforms set PLAT_XLAT_TABLES_DYNAMIC=0 and
define it unconditionally also in platform Makefiles.
Due to this when PLAT_XLAT_TABLES_DYNAMIC=0 the limits for
MAX_PHYS_ADDR is wrongly set to the whole physical address space size.
Instead of definition the value of PLAT_XLAT_TABLES_DYNAMIC is checked
to set MAX_PHYS_ADDR to total mapped physical region.

Reference: plat/nvidia/tegra/platform.mk

Change-Id: I7bd786aaa4b039951341d0337f694074345f717f
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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docs: add TF-A version numbering information

Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is

docs: add TF-A version numbering information

Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is used for LTS releases. A comment for this macro is also
added in Makefile.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I946b6cb91bb8454131f07b24534d28ab1aef1771

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feat(morello): add TF-A version string to NT_FW_CONFIG

TF-A version string is passed into NT_FW_CONFIG to allow access in
UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I9da7b9

feat(morello): add TF-A version string to NT_FW_CONFIG

TF-A version string is passed into NT_FW_CONFIG to allow access in
UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I9da7b93d30c9d9230ea9a2cd2730cde897ffc580

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feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

SDS firmware version structure is added with MCC, PCC and SCP firmware
version members. These are set in NT_FW_CONFIG to provi

feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

SDS firmware version structure is added with MCC, PCC and SCP firmware
version members. These are set in NT_FW_CONFIG to provide access to
firmware version information in UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: Ib0c476e54ef428fb7904f0de5c6f4df6a5fbd7db

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feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-o

feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "fix(rmmd): enable sme using sme_enable_per_world" into integration

fix(rmmd): enable sme using sme_enable_per_world

Enable SME for RMM using sme_enable_per_world as well as sme_enable.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id:

fix(rmmd): enable sme using sme_enable_per_world

Enable SME for RMM using sme_enable_per_world as well as sme_enable.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I6070f4778e507ac9cbc7442e727bedad9b40e635

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fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55

fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[5

fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to

fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge "fix(build): remove duplicated include order" into integration

Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict low

Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths

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Merge "docs: deletion of a few deprecated platforms not yet confirmed" into integration

docs(versal-net): add TSP build documentation

Add information about Versal NET platform for TSP and provide
the build commands.

Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: P

docs(versal-net): add TSP build documentation

Add information about Versal NET platform for TSP and provide
the build commands.

Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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docs(versal): add TSP build documentation

Add information about Versal platform for TSP and provide
the build commands.

Change-Id: I7106ab477a881c58e1c45863bd6854d188982282
Signed-off-by: Prasad Ku

docs(versal): add TSP build documentation

Add information about Versal platform for TSP and provide
the build commands.

Change-Id: I7106ab477a881c58e1c45863bd6854d188982282
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execut

feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.

The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.

Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution envi

feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-
EL1 Payload Dispatcher (SPD) service called TSPD, this service
is responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of
BL32 once the runtime services are fully initialized. BL31 invokes
such a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3
This is because the S-EL1 can use GIC system registers to manage
interrupts and does not need GIC interface base addresses to be
configured.

The secure code load address is initially being pointed to 0x0
in the handoff parameters, which is different from the default
or user-provided load address of 0x60000000. In this case, set up
the PC to the requested BL32_BASE address to ensure that the secure
code is loaded and executed from the correct location.

Change-Id: Ida0fc6467a10bfde8927ff9b3755a83f3e16f068
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by:

refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove

Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove extra core counts in cluster 2 and 3

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fix(build): remove duplicated include order

Commit(3547270f5 refactor(build): reorder platform Makefile
evaluation) re-ordered platform makefile inclusion before
arch_features evaluations, but then

fix(build): remove duplicated include order

Commit(3547270f5 refactor(build): reorder platform Makefile
evaluation) re-ordered platform makefile inclusion before
arch_features evaluations, but then it fails to remove the dependency
that were moved and thus have double evaluation of some build
variables apparently this breaks BUILD_PLAT.

Additionally remove duplicate checks in SPMD similar checks are in
place in main level makefile.

Change-Id: I5a71624fc43977054467ec6502ce359fb1d08838
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(sdei): ensure that interrupt ID is valid

As per SDEI spec (section 5.1.14.1), SDEI_INTERRUPT_BIND interface
expects a valid PPI or SPI. SGI's are not allowed to be bounded.
Current check in the

fix(sdei): ensure that interrupt ID is valid

As per SDEI spec (section 5.1.14.1), SDEI_INTERRUPT_BIND interface
expects a valid PPI or SPI. SGI's are not allowed to be bounded.
Current check in the code only checks for an SGI and returns invalid
ID. This check is insufficient as it will not catch architecturally
invalid interrupt IDs.

Modify the check to ensure that interrupt is either PPI or SPI.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I52eb0a6d7f88a12f6816cff9b68fb3a7ca12cbb7

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Merge "fix(tegra): return correct error code for plat_core_pos_by_mpidr" into integration

fix(tegra): return correct error code for plat_core_pos_by_mpidr

The error code for plat_core_pos_by_mpidr() for an invalid mpidr should
be -1 as mandated by portig guide, but for tegra t186 return

fix(tegra): return correct error code for plat_core_pos_by_mpidr

The error code for plat_core_pos_by_mpidr() for an invalid mpidr should
be -1 as mandated by portig guide, but for tegra t186 return value is
PSCI_E_NOT_PRESENT (-7) even though the comment at top of function says
that it should return -1.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2b69bc1a56f7966f21b2a3c89c515ebde41e3eb8

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docs(ras): update RAS documentation

Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.

Signed-off-by: Manish Pandey <manis

docs(ras): update RAS documentation

Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iedc8c1e713dad05baadd58e5752df36fa00121a7

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