Merge "feat(qemu-sbsa): mpidr needs to be present" into integration

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign

feat(intel): enable query of fip offset on RSU

Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform

Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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feat(intel): support query of fip offset using RSU

Query the fip binary from SPT table on RSU boot on Intel Agilex series.

Change-Id: I8856b49539f33272625d4c0a8c26b81b5864c4eb
Signed-off-by: Mahesh

feat(intel): support query of fip offset using RSU

Query the fip binary from SPT table on RSU boot on Intel Agilex series.

Change-Id: I8856b49539f33272625d4c0a8c26b81b5864c4eb
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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fix(xilinx): deprecate SiP service count query

As per SMCCC Section 6.2, the call count query for all the services
has been deprecated from SMCCC v1.2 onwards.

Inline with above change, AMD-Xilinx

fix(xilinx): deprecate SiP service count query

As per SMCCC Section 6.2, the call count query for all the services
has been deprecated from SMCCC v1.2 onwards.

Inline with above change, AMD-Xilinx SiP service count query has
been deprecated and now onwards will return unknown function
identifier error.

Change-Id: I296d119d65549fdb01718d08351d255550e4ead0
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(qemu-sbsa): mpidr needs to be present

Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.

No MPIDR == panic() in case w

feat(qemu-sbsa): mpidr needs to be present

Coverity Scan reminded that we need to take care of MPIDR properly.
We need to make sure that we get MPIDR values from QEMU.

No MPIDR == panic() in case which should not happen.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Idb5fe7d958f0bcecd3d66a643743f478538f4a8b

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Merge "fix(spm): not defining load-address in SP config" into integration

fix(rockchip): fix documentation in how build bl31 in AARCH64

Rockchip Aarch64 SoCs expect TF-A's BL31

Change-Id: Ie74be32e2bd24c4de38990791b4a03d2b7695b4d
Signed-off-by: Michael Trimarchi <michael

fix(rockchip): fix documentation in how build bl31 in AARCH64

Rockchip Aarch64 SoCs expect TF-A's BL31

Change-Id: Ie74be32e2bd24c4de38990791b4a03d2b7695b4d
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>

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docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I7

docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I753287feec1cd459edfd3d1c103e0e701827cc05
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(ti): do not stop non-secure timer on world switch

As stated in the commit introducing the NS_TIMER_SWITCH build flag,
saving/restoring this registers causes the non-secure timer to stop
while in

fix(ti): do not stop non-secure timer on world switch

As stated in the commit introducing the NS_TIMER_SWITCH build flag,
saving/restoring this registers causes the non-secure timer to stop
while in the secure world and non-secure timer interrupts are prevented
from asserting until we return to the non-secure world. This breaks
any realtime OS on the non-secure side that uses this timer for
realtime scheduling.

This flag is by default off, but OP-TEE SPD enables it. The K3 OP-TEE
platform makes no use of these registers and we would like to have
support for realtime OSs while also supporting the OP-TEE SPD. Disable
this flag in our platform definition.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I65055512d897b93b7690fd63c734f4731a6e09e6

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feat(stm32mp2): put back core 1 in wfi after debugger's halt

The core 1 is put in wfi for pen holding. If a debugger halts the
core, it causes the core to exit from wfi.

Let the core to jump back i

feat(stm32mp2): put back core 1 in wfi after debugger's halt

The core 1 is put in wfi for pen holding. If a debugger halts the
core, it causes the core to exit from wfi.

Let the core to jump back in wfi when the debugger resumes the
core's execution.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Change-Id: I9b5607b05cdcde905dc4047af8d6f1292d53d701

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feat(stm32mp2): add plat_my_core_pos

This function is required, at least for bakery locks.

Change-Id: I28906c50e0a0ebff5d387a424247513ec1a599fc
Signed-off-by: Yann Gautier <yann.gautier@st.com>

fix(stm32mp2): correct early/crash console init

The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep

fix(stm32mp2): correct early/crash console init

The former code, using x2 register, was removing the LPEN bit from UART
config register. So the UART clock is stopped as soon as the CA35 is in
CSleep. It was then displaying crap in Linux console.
The ands check instruction is replaced with a clearer tst instruction
directly with the bit to be tested.

Change-Id: I8a2b3ab195981dee2962e0c2f5d501d5933c17f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "fix(memmap): fix footprint free space calculation" into integration

fix(memmap): fix footprint free space calculation

Calculate the free space as the range between the
limit and the end of the memory region *_REGION_END.

Change-Id: I9cacadea2543c9f5ddaebca82344a836

fix(memmap): fix footprint free space calculation

Calculate the free space as the range between the
limit and the end of the memory region *_REGION_END.

Change-Id: I9cacadea2543c9f5ddaebca82344a83678cd7d55
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "drop-dt-from-edk2/cpu" into integration

* changes:
docs(qemu-sbsa): describe what we get from QEMU
feat(qemu-sbsa): handle CPU information

fix(spm): not defining load-address in SP config

The FF-A specification has made it such that SPs
may optionally specify their load address in the manifest.

This info was being retrieved to generat

fix(spm): not defining load-address in SP config

The FF-A specification has made it such that SPs
may optionally specify their load address in the manifest.

This info was being retrieved to generate some information
for the SPMC manifest. However, it is not a mandatory utility.

This change relaxes the case in which the SP manifest doesn't
have a load address.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ic4c1b1ec6666522900c113903be45ba0eb5d0bf6

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docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firm

docs(qemu-sbsa): describe what we get from QEMU

QEMU provides us with minimal information about hardware platform using
minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even
a firmware DeviceTree.

Change-Id: I7b6cc5f53a4f78a9ed69bc7fc2fa1a69ea65428d
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets

feat(qemu-sbsa): handle CPU information

We want to remove use of DeviceTree from EDK2. So we move
functions to TF-A:

- counting cpu cores
- checking NUMA node id
- checking MPIDR

And then it gets passed to EDK2 via SMC calls.

Change-Id: I1c7fc234ba90ba32433b6e4aa2cf127f26da00fd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge "fix(context-mgmt): align the memory address of EL2 context registers" into integration

Merge "feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE" into integration

Merge "feat(intel): support wipe DDR after calibration" into integration

Merge "fix(intel): update from INFO to VERBOSE when print debug message" into integration

fix(context-mgmt): align the memory address of EL2 context registers

EL2 registers are 8 byte wide and are allocated continuous memory.
After moving MPAM_EL2 registers out of the EL2 struct, the sec

fix(context-mgmt): align the memory address of EL2 context registers

EL2 registers are 8 byte wide and are allocated continuous memory.
After moving MPAM_EL2 registers out of the EL2 struct, the section
of memory, assigned to MPAM registers in EL2 registers structure has
to be removed.

Henceforth, this patch addresses this issue and cleans up the unsued memory.

Change-Id: I3425b43add0755ff1f5cb803cd5fa667082e7814
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and

feat(versal): extend platform address space sizes

The AMD-Xilinx Versal platform, currently only supports the OCM and
Low DDR address ranges in both physical and virtual address range.
To locate and execute TF-A from High DDR and HBM address range,
expanding the address scope is necessary.

Depending on the BL31_BASE address both the platform physical and
virtual space sizes are selected.

Change-Id: I49112bff9eda44d924c5f49ea99aed9a8d5e5774
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes Id85b2541,I4d253e2f into integration

* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock