chore(libfdt): update header files to v1.7.0 tag

As part of TF-A 2.9.0 release, libfdt version was updated to its last
tagged version (1.7.0) with commit 058e017e5. This commit has only
updated the

chore(libfdt): update header files to v1.7.0 tag

As part of TF-A 2.9.0 release, libfdt version was updated to its last
tagged version (1.7.0) with commit 058e017e5. This commit has only
updated the source files of libfdt but did not update header files.

This patch updates the libfdt header files in include/lib/libfdt to
the tagged version v1.7.0

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I09a0f51435b343c3e1cac45075fe7d28cbcae867

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fix(smccc): ensure that mpidr passed through SMC is valid

There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr v

fix(smccc): ensure that mpidr passed through SMC is valid

There are various SMC calls which pass mpidr as an argument which is
currently tested at random places in SMC call path.
To make the mpidr validation check consistent across SMC calls, do
this check as part of SMC argument validation.

This patch introduce a helper function is_valid_mpidr() to validate
mpidr and call it as part of validating SMC arguments at starting of
SMC handlers (which expect mpidr as an argument).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I11ea50e22caf17896cf4b2059b87029b2ba136b1

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fix(build): don't generate build-id

1. build-id takes space in memory
2. in some cases for lto build linker decided to put new
.note.gnu.build-id section before .text section. The result was
non-wor

fix(build): don't generate build-id

1. build-id takes space in memory
2. in some cases for lto build linker decided to put new
.note.gnu.build-id section before .text section. The result was
non-working image, because entry point wasn't at __BLXX_START__
anymore.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: Id78ccbc51e5ef82296069444ab438a1964a74e78

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fix(build): add forgotten BL_LDFLAGS to lto command line

as a result of missing BL_LDFLAGS '-Wl,--sort-section=alignment' was
missing in link arguments for bl31.

Signed-off-by: Andrey Skvortsov <an

fix(build): add forgotten BL_LDFLAGS to lto command line

as a result of missing BL_LDFLAGS '-Wl,--sort-section=alignment' was
missing in link arguments for bl31.

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: I78878e49da21fdc565abb3072e4abaf9face49f4

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feat(build): check that .text section starts at page boundary

Linker may decide to put new unspecified sections before .text
section. That will cause non-working image, because entry point isn't
at

feat(build): check that .text section starts at page boundary

Linker may decide to put new unspecified sections before .text
section. That will cause non-working image, because entry point isn't
at __BLXX_START__. Device just not booted with such image.

This happened for example with .note.gnu.build-id section generated
for LTO build in some cases. Now linker will report this situation as
an error.

```
/usr/lib/gcc-cross/aarch64-linux-gnu/13/../../../../aarch64-linux-gnu/bin/ld: .text is not aligned on a page boundary.
collect2: error: ld returned 1 exit status
```

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: I5ae46ddd1e6e431e1df1715d1d301f6dd7181cc7

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build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d8

build(qemu-sbsa): it is GICv3 platform

GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895

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Merge "fix(sdei): ensure that interrupt ID is valid" into integration

Merge changes from topic "enable_assertion" into integration

* changes:
feat(zynqmp): enable assertion
feat(versal-net): enable assertion
feat(versal): enable assertion

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround fo

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround for Neoverse N2 erratum 2340933
fix(cpus): workaround for Neoverse N2 erratum 2346952

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Merge "fix(ti): release lock in all TI-SCI xfer return paths" into integration

Merge "feat(xilinx): switch boot console to runtime" into integration

Merge "docs: add TF-A version numbering information" into integration

Merge "feat(zynqmp): remove pm_ioctl_set_sgmii_mode api" into integration

fix(ti): release lock in all TI-SCI xfer return paths

Failing to send a message is often not fatal and we will end up trying
to send again. This would fail as some exit paths do not release the
secu

fix(ti): release lock in all TI-SCI xfer return paths

Failing to send a message is often not fatal and we will end up trying
to send again. This would fail as some exit paths do not release the
secure proxy xfer lock. Release this lock on all return paths.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I3939015774f819572dbd26720b2c105fba7574cb

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fix(intel): bl31 overwrite OCRAM configuration

U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.

Change

fix(intel): bl31 overwrite OCRAM configuration

U-boot is allowed to configure OCRAM access. However
ATF BL31 will overwrite it. Thus removing this function
to allow for proper configuration.

Change-Id: I45173ef8f472c3620486de0cbf6452ba5f78be01
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when F2SOC is executed, the "return" result will overwrite
SOC2FPGA "return" result even though it is not enabled.
Using 2 different "return" result to for each bridges and
return both of them at the end of the function to
avoid being overwritten.

Change-Id: Id9de3f416fe3020db35bc946135b175be2a7dc1e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.

Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-

fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404

fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404b8449b0c3f69
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge changes from topic "morello/firmware-revision" into integration

* changes:
feat(morello): add TF-A version string to NT_FW_CONFIG
feat(morello): set NT_FW_CONFIG properties for MCC, PCC an

Merge changes from topic "morello/firmware-revision" into integration

* changes:
feat(morello): add TF-A version string to NT_FW_CONFIG
feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

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Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name

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fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA

fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC

Change-Id: Ia539ff289e83303ae3b4d78b9ac1d50c9f9558da
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): temporarily workaround for Zephyr SMP

Temporarily workaround for Zephyr SMP testing.

Change-Id: I9d2d209e9f384d079f0311b3a8b0b760e0566877
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@int

fix(intel): temporarily workaround for Zephyr SMP

Temporarily workaround for Zephyr SMP testing.

Change-Id: I9d2d209e9f384d079f0311b3a8b0b760e0566877
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id

fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id: I45ebfdcc17c47bcce69f5f611e677ac7838ecf52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain

feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain for those common
declaration.

Change-Id: Ibb640f08ac313bbad6d9295596cb8ff26e3e626d
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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