Merge "fix(cpus): workaround for Neoverse V2 erratum 2618597" into integration

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use

fix(cpus): workaround for Neoverse V2 erratum 2618597

Neoverse V2 erratum 2618597 is a Cat B erratum that applies to
all revisions <= r0p1 and is fixed in r0p2. The workaround is to
disable the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: I23a81275d1e40cae39e6897093d6cdd3e11c08ea
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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feat(libc): add printf support for space padding

This patch makes printf capable of padding strings with spaces
to their left, allowing right-aligning numeric values and strings.
It uses the same wi

feat(libc): add printf support for space padding

This patch makes printf capable of padding strings with spaces
to their left, allowing right-aligning numeric values and strings.
It uses the same width field for the format specifier as in the
original libc function : %<width><type> (e.g.: %10d pads an
integer value with spaces to the left to complete 10 characters).

Change-Id: Ib7b5519dae17742181352ce58e507a05ba5250d4
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nish

feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I9f1a6825d43f8be1c4bdeb98d9d7267b595e2b76

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feat(fvp): add stdout-path

Add stdout-path to the fvp-base devicetree to be passed to BL33 (U-Boot)
and then to the Linux kernel to be compliant to Arm SystemReady IR:
https://developer.arm.com/docu

feat(fvp): add stdout-path

Add stdout-path to the fvp-base devicetree to be passed to BL33 (U-Boot)
and then to the Linux kernel to be compliant to Arm SystemReady IR:
https://developer.arm.com/documentation/DUI1101/2-0/
Configure-U-Boot-for-SystemReady/Adapt-the-Devicetree

This has been tested by booting fvp-base to Linux and ensuring the
console is accessible.

Change-Id: Iae98630f18f735ce344c1158f41f358c2a49eeb6
Signed-off-by: Diego Sueiro <Diego.Sueiro@arm.com>
Signed-off-by: Debbie Martin <Debbie.Martin@arm.com>

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Merge "fix(cpus): workaround for Neoverse V2 erratum 2662553" into integration

Merge "feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag" into integration

Merge "fix(docs): revise the description of REGISTER_CRYPTO_LIB" into integration

feat(el3-spmc): synchronize access to the s-el0 sp context

This patch locks and unlocks access to the S-EL0 SP context when its
runtime state and model are updated to avoid issues around concurrent

feat(el3-spmc): synchronize access to the s-el0 sp context

This patch locks and unlocks access to the S-EL0 SP context when its
runtime state and model are updated to avoid issues around concurrent
access to global state.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I427657050574c189cbaf82c1371e3ee44bc1663e

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feat(el3-spmc): add support to map S-EL0 SP device regions

Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.

SP running at SEL-0 does not have enough

feat(el3-spmc): add support to map S-EL0 SP device regions

Add the support to parse SP manifest to get device regions, create xlat
table entries for the SP.

SP running at SEL-0 does not have enough privilege to map the regions
itself.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I600f51ee62a33443fe7f1c4e007cc6c5ab45222f

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feat(el3-spmc): add support to map S-EL0 SP memory regions

Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.

SP manifest contains the info

feat(el3-spmc): add support to map S-EL0 SP memory regions

Add the support to parse SP manifest to get memory regions, create xlat
tables and then program it in TTBR0.

SP manifest contains the info on memory map regions that are needed by
the SP. These regions needs to be mapped as SP running at S-EL0 does not
have privilege to do it.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I0cad36e5c43f8a68c94887ff2bd798933a26be27

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feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs

Secure partition running at SEL0 does not have privilege to modify
translation tables. So it needs SPMC to map the regions for it. Add t

feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs

Secure partition running at SEL0 does not have privilege to modify
translation tables. So it needs SPMC to map the regions for it. Add the
support to request memory map or region info using FF-A interface.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Change-Id: I04a97899808bbd45eda24edf7bc74eaef96fb2ce

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feat(el3-spmc): add support to setup S-EL0 context

Add support to setup S-EL0 context by setting up the following

S-EL1 shim exception handlers: This is a trampoline between S-EL0 and

feat(el3-spmc): add support to setup S-EL0 context

Add support to setup S-EL0 context by setting up the following

S-EL1 shim exception handlers: This is a trampoline between S-EL0 and
monitor running at EL3 and is used to
handle or forward exceptions from S-EL0.

Boot Info region: This region holds the boot protocol data that is
passed between SPMC and SP.

Setup system registers: Setup sctlr_el1, vbar_el1, cntkctl_el1,
ctx_cpacr_el1(enable fp and smid), spsr and
sp_el0

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I82d21fcd95529f235bee8bf838d36a2ac519bb0a

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feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'

feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'NEOVERSE_Nx_EXTERNAL_LLC' for all the Neoverse reference design
platforms.

Change-Id: I813b3ef7ea7dc4e335b44a88e019d8c56f05f4ac
Signed-off-by: Nuno Lopes <nuno.lopes@arm.com>

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Merge "fix(rk3328): apply ERRATA_A53_1530924 erratum" into integration

fix(docs): revise the description of REGISTER_CRYPTO_LIB

verify_hash should be placed before calc_hash
align with crypto_mod.h

Change-Id: I536125502d83bb732cf70fbe516d5fe009dc95fe
Signed-off-by: zh

fix(docs): revise the description of REGISTER_CRYPTO_LIB

verify_hash should be placed before calc_hash
align with crypto_mod.h

Change-Id: I536125502d83bb732cf70fbe516d5fe009dc95fe
Signed-off-by: zhiyang.shi <zhiyang.shi@cixtech.com>

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Merge "feat(security): add support for SLS mitigation" into integration

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image ch

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image check in prepare_dtb

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Merge "fix(intel): read QSPI bank buffer data in bytes" into integration

Merge "fix(intel): temporarily workaround for Zephyr SMP" into integration

Merge "feat(intel): restructure watchdog" into integration

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workarou

Merge changes from topic "sm/errata" into integration

* changes:
fix(cpus): workaround for Cortex-A78C erratum 2743232
fix(cpus): workaround for Neoverse V1 erratum 2348377
fix(cpus): workaround for Cortex-X3 erratum 2779509

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fix(rk3328): apply ERRATA_A53_1530924 erratum

Apply erratum ERRATA_A53_1530924.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib4130fd9d4cd16b12322f44e91196607fcb6bf6b

Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

Merge "feat(intel): increase bl2 size limit" into integration