feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@in

feat(intel): add in QSPI ECC for Linux

Add QSPI ECC new opcodes for Linux to access to SDM register

Change-Id: If9ac35afdddb91db6bad6b474060cd001f6d89e6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@

fix(intel): add HPS remapper to remap base address for SDM

Remap base address for SDM to access DRAM.

Change-Id: If064bd1ff4571d3217b136d9b5ebbfdecb68231e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "refactor(cm): move MPAM3_EL3 reg to per world context" into integration

docs: update links to tf.org-wide process documents

tf.org-wide documents have been migrated away from
developer.trustedfirmware.org, because the latter will be
decomissioned at some point in the fu

docs: update links to tf.org-wide process documents

tf.org-wide documents have been migrated away from
developer.trustedfirmware.org, because the latter will be
decomissioned at some point in the future. These documents are now
hosted in a new 'tf_docs' repository hosted on Github [1] and can be
easily browsed through a new ReadTheDocs website at [2].

Update all relevant links in TF-A documentation to refer to [2].

[1] https://github.com/TrustedFirmware/tf_docs
[2] https://trusted-firmware-docs.readthedocs.io/

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Ib9d39c36250a05754fe5e46cb6f3044ecb776534

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refactor(cm): move MPAM3_EL3 reg to per world context

Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.

Signed-off-by: Arvind

refactor(cm): move MPAM3_EL3 reg to per world context

Refactor MPAM3_EL3 to be world-specific, eliminating redundant cross-CPU
value duplication and reducing memory footprint.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Iddf020a5462737e01ac35e4f2b2b204a8759fafb

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fix(cpus): workaround for Cortex X3 erratum 2743088

Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instructio

fix(cpus): workaround for Cortex X3 erratum 2743088

Cortex X3 erratum 2743088 is a Cat B erratum that applies to all
revisions <= r1p1 and is fixed in r1p2. The workaround is to add a DSB
instruction before the ISB of the powerdown code sequence specified in
the TRM.

SDEN documentation: https://developer.arm.com/documentation/2055130

Change-Id: I2c8577e3ca0781af8b1c3912e577d3bd77f92709
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge "refactor(cm): reset the cptr_el3 before perworld context setup" into integration

Merge changes from topic "xlnx_enable_errata" into integration

* changes:
docs(versal): add ERRATA_ABI_SUPPORT build documentation
feat(versal): enable errata management feature

docs(versal): add ERRATA_ABI_SUPPORT build documentation

Add information about Versal platform for ERRATA_ABI_SUPPORT and
provide the build commands.

Signed-off-by: Prasad Kummari <prasad.kummari@a

docs(versal): add ERRATA_ABI_SUPPORT build documentation

Add information about Versal platform for ERRATA_ABI_SUPPORT and
provide the build commands.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I8466ea446814f888ae56f5cbb7bbdc06099d54f8

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feat(versal): enable errata management feature

The errata ABI feature-specific build flag, the flag enabling CPUs
in the CPU list, and the flags testing non-ARM interconnect-based
errata when enable

feat(versal): enable errata management feature

The errata ABI feature-specific build flag, the flag enabling CPUs
in the CPU list, and the flags testing non-ARM interconnect-based
errata when enabled from a platform level are added to the AMD-Xilinx
Versal platform makefile to assess the errata ABI feature
implementation.

ERRATA_ABI_SUPPORT : Boolean option to enable support for Errata
management firmware interface for the BL31 image. By default,
its disabled set to zero.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I54cda23d699abc0782f44172c28933f5cbb010b8

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refactor(cm): reset the cptr_el3 before perworld context setup

Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
t

refactor(cm): reset the cptr_el3 before perworld context setup

Currently, the registers which are maintained per-world, does not
take into account the reset value while configuring the context for
the respective world.
This leads to an issue, wherein the register retains the same value
across world switch, which is an error.

This patch addresses this problem, by configuring the register
(cptr_el3) precisely according to the world, the cpu is in
execution via resetting it before initializing the world specific context.

Change-Id: I592d82af373155fca67eed109c199341c305f0b9
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration

Merge "fix(intel): bl31 overwrite OCRAM configuration" into integration

Merge "fix(intel): update DDR range checking for Agilex5" into integration

Merge "fix(intel): update fcs functions to check ddr range" into integration

Merge "fix(cpus): workaround for Cortex-A520 erratum 2858100" into integration

Merge "fix(errata): add Cortex-A520 definitions" into integration

fix(cpus): workaround for Cortex-A520 erratum 2858100

Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUAC

fix(cpus): workaround for Cortex-A520 erratum 2858100

Cortex-A520 erratum 2858100 is a Cat B erratum that applies to
all revisions <=r0p1 and is still open. The workaround is to
set bit[29] of CPUACTLR_EL1.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2444153/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5a07163f919352583b03328abd5659bf7b268677

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fix(errata): add Cortex-A520 definitions

Include the missing Cortex-A520 header.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I45153a1aa2d6dace38650268a32106f5201f48bd

Merge "fix(cpus): fix incorrect AMU trap settings for N2 CPU" into integration

Merge "feat(intel): support SDM mailbox safe inject seu error for Linux" into integration

Merge "feat(handoff): enhance transfer list library" into integration

feat(handoff): enhance transfer list library

Define new transfer entry TL_TAG_OPTEE_PAGABLE_PART for OP-TEE.
Add API for achieving handoff args from transfer entries.
Add API for dumping the transfe

feat(handoff): enhance transfer list library

Define new transfer entry TL_TAG_OPTEE_PAGABLE_PART for OP-TEE.
Add API for achieving handoff args from transfer entries.
Add API for dumping the transfer list.
Add tl->flags, tl->reserved and TL_FLAGS_HAS_CHECKSUM to align to
the spec update.
Update TL signature to 4a0f_b10b to align to the spec update.
Minor fixes for the coding and comment style.

Change-Id: I0e159672e4ef4c50576f70b82e1b7bae08407acc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR f

feat(intel): enable SDMMC frontdoor load for ATF->Linux

SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.

Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06a

fix(intel): fix hardcoded mpu frequency ticks

This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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