feat(tc): choose the DPU address and irq based on the target

Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547

feat(tc): choose the DPU address and irq based on the target

Currently there are two configurations for DPU
Config 1: Address - 0x2CC0_0000 IRQ - 101
Config 2: Address - 0x40_0000_0000 IRQ - 547

Config 1 is used by all FPGA and TC0, TC1 and TC2 FVPs
Config 2 is used by TC3 FVP currently

Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: If0097441b6ab90f58911df032e45f6bf06fc7909

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feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU

feat(tc): add SCMI power domain and IOMMU toggles

Compile-time controls have been added for the following:

* SCMI power domain use for DPU and GPU.
* SMMU-700: planned rework required to use IOMMU correctly
for DPU and GPU.

These will allow easier experimentation in the future without
ad-hoc changes needed in the dts file for any sort of analysis
that requires testing different paths.

For TC3 however, the DPU is in an always on power domain so SCMI power
domains are not supported.

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Change-Id: If6179a3e4784c1b69f0338a8d52b552452c0eac1

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refactor(tc): move the FVP RoS to a separate file

In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to t

refactor(tc): move the FVP RoS to a separate file

In trying to use the same DTS for the FVP and FPGA subvariants we need
to keep track of what is different. Move the FVP RoS, which is different
to the FPGA's, to reduce the number of ifdefs and make FVP-only changes
easier.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ib7999d3e39de55ab4a30e68dd81f95120be15a8c

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feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The dif

feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
* addresses of GIC and UART
* displays (FPGA uses 4k)
* ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

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feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arran

feat(tc): introduce an FPGA subvariant and TC3 CPUs

TC is getting an FPGA port alongside the FVP. It is meant to be
identical, but the core configurations on TC2 differ (there are 14 in an
odd arrangement).

Introduce these differences and gate them behind a new TARGET_FLAVOUR
flag which defaults to FVP for compatibility.

While updating CPUs, it's a good time to do TC3 too. It has different
cores in a different configuration again, so it needs different capacity
values. Those have been derived using GeekBench 6.0 ST on the FPGA.

Finally GPU and DPU power domains are 1 above the CPUs so make that
relative.

In the end, the big/mid/little configurations are:
* TC2 FVP: 1/3/4
* TC2 FPGA: 2/3/5/4 (the 3 is a big "min" core)
* TC3 both: 2/4/2 (with new capacities)

Co-developed-by: Tintu Thomas <tintu.thomas@arm.com>
Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I3c3a10d6727f5010fd9026a404df27e9262dff6b

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feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utili

feat(tc): add TC3 platform definitions

TC3 is a little different from TC2:

* new address for its second DRAM bank
* new CPUs
* a few interrupts have changed
* new SCP MHU base address.
* utility space address (needed for MPAM) is different
* no CMN (and therefore cmn-pmu)
* the uart clock is different

This requires the dts to be different between revisions for the first
time. Introduce a tc_vers.dtsi that includes only definitions for things
that are different.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827

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refactor(tc): sanitise the device tree

We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.

Do this by renaming nodes to co

refactor(tc): sanitise the device tree

We have lots of errors in our device tree when running dt-validate.
Remove the majority so that dt-validate-ing is useful now.

Do this by renaming nodes to conform to spec, making addresses lowercase
with no 0x at the front, and removing nodes that shouldn't be there.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1840f0f5de34a56ee240c07eff08d73c856b338e

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feat(tc): add PMU entry

TC has PMUs with interrupts in all cores and Linux needs to be told
about them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668

feat(tc): add PMU entry

TC has PMUs with interrupts in all cores and Linux needs to be told
about them.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice0e6dab396b90c05f4b9668623ba7b3556a53ac

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feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRA

feat(tc): allow booting from DRAM

In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRAM1 bank. If we want to access it it needs
to be mapped to memory.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I45e0fbb016e8f615d41b6ad9da0d1e7b466ece72

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docs(auth): align TBBR CoT names to match the code

Update the section describing the TBBR chain of trust to use the same
terminology as in the code and the specification.

Also refresh the descripti

docs(auth): align TBBR CoT names to match the code

Update the section describing the TBBR chain of trust to use the same
terminology as in the code and the specification.

Also refresh the description of some of the certificates to include the
pieces of data they contain today. When this document was originally
written, TF-A did not support configuration files, which is why none of
the certificates included any configuration file hash at that time.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia85f88c933abd8d8d6727252a7d41fb9f0ce4287

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Merge "refactor(st-i2c): use fdt_read_uint32_default()" into integration

Merge "build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag" into integration

docs(versal-net): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id:

docs(versal-net): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I4bd71dd8e16c7adf3f9c5cb202f36aa2e275d03a

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docs(versal): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic2

docs(versal): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ic232551bb09152124da5226673c88e1a34a384c4

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docs(zynqmp): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I89

docs(zynqmp): update SMC convention

Updated documentation for SMC SiP calling conventions for IPI,
PM, and SiP Service queries.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I8904628d41b47596257f06791bffb7cde35879de

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build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga wi

build(fpga): correctly handle gcc as linker for LTO

When LTO is enabled and gcc is used as a linker, then option for a
linker have to be provided with a -Wl prefix to gcc.

To build PLAT=arm_fpga with LTO enabled extra '-nostdlib' has to be
supplied to the linker at least, otherwise build fails with an error
about many undefined references in libc.
Since this option is defined as part of common TF_LDFLAGS already,
just use that variable with couple extra options.

Change-Id: Iaab72d894317c91af5b7d770652e4353b32aae88
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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fix(build): enforce single partition for LTO build

For example, build for PLAT=fvp SPD=spmd fails with a following error
when LTO is enabled using GCC 13.2.1:

aarch64-none-elf/bin/ld: /tmp/ccrG0Z

fix(build): enforce single partition for LTO build

For example, build for PLAT=fvp SPD=spmd fails with a following error
when LTO is enabled using GCC 13.2.1:

aarch64-none-elf/bin/ld: /tmp/ccrG0Z8D.ltrans0.ltrans.o: in function `spmd_smc_forward':
arm-trusted-firmware/services/std_svc/spmd/spmd_main.c:749:(.text+0xbe50): undefined reference to `rdist_ctx'
aarch64-none-elf/bin/ld: arm-trusted-firmware/services/std_svc/spmd/spmd_main.c:749:(.text+0xbe58): undefined reference to `dist_ctx'
collect2: error: ld returned 1 exit status

Access to rdist_ctx and dist_ctx is defined using inline assembler
like
__asm__ volatile ("ldr %0, =rdist_ctx" : "=r" (v) : "X" (rdist_ctx));

Access assembler function definitions moved to a different ltrans then
actual variables. Partitioner doesn't take into account defined and
used symbols in inline assembler. Depending on compiler partitioner
decision the same code builds for some platforms successfully.

This is a known gcc problem
1. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=57703
2. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=46820

TF-A source code isn't that big and enforcing single partitioning will
not affect build performance, but will fix problems with 'undefined
references' related to inline assembler.

Change-Id: I72955ab0318f72b588d3a246824f99a48a92d8ef
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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fix(rockchip): add support for building with LTO enabled

Using the asm .incbin statement in C sources breaks gcc wrapper.
Build fails with a following errors:
/tmp/ccRXHTU4.s: Assembler messages:

fix(rockchip): add support for building with LTO enabled

Using the asm .incbin statement in C sources breaks gcc wrapper.
Build fails with a following errors:
/tmp/ccRXHTU4.s: Assembler messages:
/tmp/ccRXHTU4.s:34: Warning: dwarf line number information for .pmusram.incbin ignored
...
/tmp/ccRXHTU4.s:2119: Warning: dwarf line number information for .pmusram.incbin ignored
/tmp/ccRXHTU4.s:112497: Error: leb128 operand is an undefined symbol: .LVU5
/tmp/ccRXHTU4.s:112498: Error: leb128 operand is an undefined symbol: .LVU6
/tmp/ccRXHTU4.s:112507: Error: leb128 operand is an undefined symbol: .LVU9
...
/tmp/ccRXHTU4.s:115407: Error: leb128 operand is an undefined symbol: .LVU668
/tmp/ccRXHTU4.s:115408: Error: leb128 operand is an undefined symbol: .LVU710
/tmp/ccRXHTU4.s:115409: Error: leb128 operand is an undefined symbol: .LVU713
lto-wrapper: fatal error: aarch64-none-elf-gcc returned 1 exit status
compilation terminated.
aarch64-none-elf/bin/ld: error: lto-wrapper failed
collect2: error: ld returned 1 exit status

Fix it in a similar way to what the Linux kernel does, see commit
919aa45e43a84d40c27c83f6117cfa6542cee14e (MODSIGN: Avoid using .incbin
in C source). [1]

1. https://lkml.org/lkml/2012/12/4/136

Change-Id: Iecc19729ce59e8c3b3c30fa37b1fddef95e83c96
Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>

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chore(tc): remove unused hdlcd

The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id:

chore(tc): remove unused hdlcd

The hdlcd device tree node is not in use for any TC incarnation. The DPU
replaces it. So drop it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5393435e36d8307bef909a6519cb40305b77f0cf

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feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total c

feat(tc): add firmware update secure partition

Firmware update is a trusted service secure partition that implements
the PSA firmware update specification. It executes in the secure world
in total compute platform. To make it fit with Op-tee we need to reduce
its available memory.

Also, reserve 4 MB for stmm communication used for firmware update.
The firmware update secure partition and u-boot communicates using the
stmm communication layer and it needs a dedicated memory region.

Co-developed-by: Sergio Alves <sergio.dasilvalves@arm.com>
Co-developed-by: Davidson K <davidson.kumaresan@arm.com>
Signed-off-by: Tudor Cretu <tudor.cretu@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I0427549845f6c7650b8ef4e450d387fe9702a847

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feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co

feat(tc): add spmc manifest with trusty sp

Add SPMC manifest with Trusty SP. Define Trusty's load address,
vcpu count, memory size.

Co-developed-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Co-developed-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I1f7d7c1c6a5ef67541097ab04670343282458aeb

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refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM info

refactor(tc): unify all the spmc manifests

The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM information separately.

This has some deliberate side effects: the test configuration gets the
full secure memory address space and drops the 0x7000000 region as that
was accidentally copied over from the FVP platform and doesn't apply to
TC.

Also optee unconditionally gets the smaller mem_size as it's been
working fine and simplifies the manifest.

Small touch up is that mem_size-s are now in hex but otherwise the same
number.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea23f9769235eea32afa374952b9a0e4f6d3e9a1

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feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to bu

feat(arm): add trusty_sp_fw_config build option

Also increase add PLAT_ARM_SP_MAX_SIZE to override the default
ARM_SP_MAX_SIZE to support Trusty image and move OPTEE_SP_FW_CONFIG
documentation to build-internals.rst as it's not externally set-able.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ief90ae9113d32265ee2200f35f3e517b7b9a4bea

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fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
dis

fix(tc): do not enable MPMM and Aux AMU counters always

There are requirements in which the MPMM and Auxiliary AMU counters have
to be disabled. Hence removing the "override" here which helps in
disabling them during the build.

Change-Id: I2c0a808d5d9968082a508a9206e34f7a57f2e33a
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>

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fix(tc): correct interrupts

The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.

While we're at it, convert all interrupts

fix(tc): correct interrupts

The gic and trbe0 are listed as active high, but the spec says they are
triggered on active low. Correct according to the spec.

While we're at it, convert all interrupts to use the macros so hopefully
no such confusion happens again.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I2fc01cf0a34b031b95219b9656b613a19a2e9b2a

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