fix(measured-boot): add missing image identifier string

The case for SPD=spmd was not handled.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I6c6f268aeb0db15d41662bea81f4a9255e1fabe9

refactor(measured-boot): move metadata size macros to a common header

The max size macros of metadata elements are shared across
multiple measured boot backends: rss-measured-boot, dpe.

Increase th

refactor(measured-boot): move metadata size macros to a common header

The max size macros of metadata elements are shared across
multiple measured boot backends: rss-measured-boot, dpe.

Increase the SW_TYPE_MAX_SIZE to be able to accomodate
all macro.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic9004a36ef1df96c70a4f7adf7bb86dc27dd307c

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refactor(measured-boot): move image identifier strings to a common header

The image identifier strings are used across different measured boot
backends. Move them to a common location to avoid the r

refactor(measured-boot): move image identifier strings to a common header

The image identifier strings are used across different measured boot
backends. Move them to a common location to avoid the redefiniton
of these per backend and to avoid code duplication.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I58897b9a19396be932ca5d230ee00858c09ef03f

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feat(st-sdmmc2): set FIFO size to 1024 on STM32MP25

On STM32MP25, a new version of the SDMMC2 IP is embedded (v3.0).
The size of the FIFO is 1024 in this new IP version.

Signed-off-by: Yann Gautier

feat(st-sdmmc2): set FIFO size to 1024 on STM32MP25

On STM32MP25, a new version of the SDMMC2 IP is embedded (v3.0).
The size of the FIFO is 1024 in this new IP version.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ie6b1fb215fc77b24b7c342d4cd69248a96039a4d

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Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi)

Merge changes from topic "sm/framework_optimize" into integration

* changes:
chore: rearrange the fvp_cpu_errata.mk file
fix(cpus): add erratum 2701951 to Cortex-X3's list
refactor(errata-abi): workaround platforms non-arm interconnect
refactor(errata-abi): optimize errata ABI using errata framework

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feat(drtm): update DRTM version to 1.0

Update DRTM version from 0.1 to 1.0.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ic37fd29e4c2de1a29c2808870addba049d488773

feat(drtm): update references to DRTM beta0

Update all references to DRTM beta0 to be 1.0 instead.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ieda70f26f3be42f4705e9b267706674c94f

feat(drtm): update references to DRTM beta0

Update all references to DRTM beta0 to be 1.0 instead.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Ieda70f26f3be42f4705e9b267706674c94f120f2

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feat(drtm): for TPM features fw hash algorithm should be 16-bits

The DRTM 1.0 spec changed the Firmware hash algorithm field
size from 32-bits to 16-bits.

Signed-off-by: Stuart Yoder <stuart.yoder@

feat(drtm): for TPM features fw hash algorithm should be 16-bits

The DRTM 1.0 spec changed the Firmware hash algorithm field
size from 32-bits to 16-bits.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I713e32e01b1983bf21d97c93bbb28c77dc94a541

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feat(drtm): add ACPI table region size to the DLME header

The DRTM 1.0 spec defines an additional field in the DLME
header for an optional region in the DLME to hold ACPI tables.

Signed-off-by: Stu

feat(drtm): add ACPI table region size to the DLME header

The DRTM 1.0 spec defines an additional field in the DLME
header for an optional region in the DLME to hold ACPI tables.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idba7fa6bd0fb4ef2bdffc24f4588720e1661e58c

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feat(drtm): update return code if secondary PE is not off

DRTM 1.0 specifies that if any secondary PEs are not off
during a dynamic launch the return code must be
SECONDARY_PE_NOT_OFF.

Signed-off-b

feat(drtm): update return code if secondary PE is not off

DRTM 1.0 specifies that if any secondary PEs are not off
during a dynamic launch the return code must be
SECONDARY_PE_NOT_OFF.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: Idcb1f3c60daa63a5bc994bdeacca8aab7066f628

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feat(drtm): add additional return codes

Add additional return codes defined in the DRTM 1.0 spec.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I1620e098edf4f070ac759a26ce3c7272faf2

feat(drtm): add additional return codes

Add additional return codes defined in the DRTM 1.0 spec.

Signed-off-by: Stuart Yoder <stuart.yoder@arm.com>
Change-Id: I1620e098edf4f070ac759a26ce3c7272faf2d8b2

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Merge "fix(el3-spmc): add datastore linker script markers" into integration

chore: rearrange the fvp_cpu_errata.mk file

Change-Id: I3959bdf5852c5714f2238f61493a931b3c857a20
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Corte

fix(cpus): add erratum 2701951 to Cortex-X3's list

Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.

SDEN documentation:
https://developer.arm.com/documentation/2055130/latest

Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level

refactor(errata-abi): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP flag. The ABI helps assist the
Kernel in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

Change-Id: Ie86b7212d731a79e2a0c07649e69234e733cd78d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structur

refactor(errata-abi): optimize errata ABI using errata framework

Errata ABI feature introduced per CPU based errata structures
in the errata_abi_main.c, these can be removed by re-using
the structures created by the errata framework.

Change-Id: I1a60d3e4f116b6254fb45426f43ff1b21771af89
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "fix(cpus): workaround for Cortex-A715 erratum 2429384" into integration

Merge "build: allow platform makefiles to configure `ENABLE_LTO`" into integration

build: allow platform makefiles to configure `ENABLE_LTO`

This change introduces a lazily-evaluated condition on `ENABLE_LTO` to
the `LTO_CFLAGS` variable as opposed to evaluating the condition
eage

build: allow platform makefiles to configure `ENABLE_LTO`

This change introduces a lazily-evaluated condition on `ENABLE_LTO` to
the `LTO_CFLAGS` variable as opposed to evaluating the condition
eagerly.

This concludes a recent request on the mailing list:

https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/EU3XR4VB3RP2NQB372QPZ4VRP57ANNLC/

Change-Id: Ie1f73352eb51fb2ceb2385232336312216ef87fc
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(maintainers): add myself as SynQuacer platform co-maintainer

Add myself as co-maintainer for SynQuacer platform,
as I'm currently working on it.

Change-Id: I149830bf7f635f72df808214e8fd23730fd

docs(maintainers): add myself as SynQuacer platform co-maintainer

Add myself as co-maintainer for SynQuacer platform,
as I'm currently working on it.

Change-Id: I149830bf7f635f72df808214e8fd23730fde7212
Signed-off-by: Masahisa Kojima <kojima.masahisa@socionext.com>

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feat(imx8m): add defines for csu_sa access security

This enables the usage of speaking defines instead of magic numbers:

CSU_SA(CSU_SA_SDMA1, 1, LOCKED)

becomes:

CSU_SA(CSU_SA_SDMA1, NON_SEC_

feat(imx8m): add defines for csu_sa access security

This enables the usage of speaking defines instead of magic numbers:

CSU_SA(CSU_SA_SDMA1, 1, LOCKED)

becomes:

CSU_SA(CSU_SA_SDMA1, NON_SEC_ACCESS, LOCKED)

Change-Id: Idcabcda677bf7840084a2ea66d321b50aa0b2b20
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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feat(imx8m): add imx csu_sa enum type defines for imx8m

This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
down

feat(imx8m): add imx csu_sa enum type defines for imx8m

This ports the missing enum defines for the central security unit found
in NXPs i.MX8M socs. The defines itself where imported from NXP's
downstream version of the trusted-firmware-a version 2.8[1].

[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4

Change-Id: Iad0c5d3733e9d29ead86334ba4bc5ce915018142
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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fix(imx8m): fix CSU_SA_REG to work with all sa registers

The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.

The defines itself was imported from

fix(imx8m): fix CSU_SA_REG to work with all sa registers

The csu found in the imx8mp has 3 csu_sa registers, before the fix not
all of them could be addressed.

The defines itself was imported from NXP's downstream version of the
trusted-firmware-a version 2.8[1].

[1]: https://github.com/nxp-imx/imx-atf/commit/0c52279fc4

Change-Id: Ia3653118bba82df9244c819a5c5f37bdc4e89c49
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>

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Merge "docs(auth): align TBBR CoT names to match the code" into integration

Merge changes from topic "css_refactor_arm" into integration

* changes:
refactor(allwinner): console runtime switch on bl31 exit
refactor(arm): console runtime switch on bl31 exit
refactor(con

Merge changes from topic "css_refactor_arm" into integration

* changes:
refactor(allwinner): console runtime switch on bl31 exit
refactor(arm): console runtime switch on bl31 exit
refactor(console): flush before console_switch_state

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