fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Ch

fix(tc): add stubs for soc_css_init functions

Add TC specific stubs for both soc_css_init_nic400 and
soc_css_init_pcie. We do not require any initialisation of these
components for TC platforms.

Change-Id: If0129acd1050a56878cb9c3041a033192c88da57
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "fix(qemu): allocate space for GPT bitlock" into integration

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and L

feat(s32g274a): enable BL2 early clocks

s32cc_init_early_clks will be used to increase the frequency of the
clocks which have a performance impact on BL2 boot. This set includes
A53, XBAR, DDR and Linflex clocks. For now, it will only contain the
frequency set for FXOSC. More clock management will be added in the next
commits.

Change-Id: Ie85465884de02f5082185f91749f190f40249c2e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "refactor(st): change method to get GIC base addresses" into integration

Merge changes Ida537d4c,Ieda75bba into integration

* changes:
build(encrypt-fw): don't generate `build_msg.c`
build(cert-create): don't generate `build_msg.c`

feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this

feat(nxp-clk): implement set_rate for oscillators

The set_rate callback will now be applied to FIRC, FXOSC, and SIRC
oscillators. It is a prerequisite for the upcoming commits that will
utilize this capability.

Change-Id: I82d1545c63b3e15497c1c002ff9ec0d7bf990aa0
Signed-off-by: Ciprian Costea <ciprianmarian.costea@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "feat(mediatek): configure DEV_IRQ as G1S interrupt" into integration

Merge "feat(ast2700): set up CPU clock frequency by SCU" into integration

feat(ast2700): set up CPU clock frequency by SCU

Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[

feat(ast2700): set up CPU clock frequency by SCU

Modify generic timer frequency by SCU setting
1. check SCU_CPU_HW_STRAP1 using HPLL or MPLL
SCU_CPU_HW_STRAP1[4]=1, using HPLL
SCU_CPU_HW_STRAP1[4]=0, using MPLL

2. read HPLL or MPLL
HPLL: frequency setting in SCU_CPU_HW_STRAP1[2:3]
MPLL: CLKIN_25M with mul and div setting from SCU_CPU_MPLL

Change-Id: I31eb10107b9da7c6746887ba36ead8ca61d86aae
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

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Merge "feat(zynqmp): enable ENABLE_LTO flag" into integration

feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b

feat(nxp-clk): add oscillator clock objects

The oscillator clock objects will be used to describe the FIRC, FXOSC,
and SIRC clocks, all of which are oscillators on S32CC SoCs.

Change-Id: Icf235cc9b8f1d95d2c0051ce9a7655fd120289b8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories

feat(nxp-clk): add minimal set of S32CC clock ids

The clock IDs are organized into categories, which are determined based
on the first 2 MSB bits for each ID. Currently, there are two big
categories: hardware and software-defined clocks.

The first category refers to clock IDs understood by the S32CC PLL muxes
and MC_CGM module muxes and is immutable. The last category of the
clocks includes software-defined IDs for clocks to allow an easy
representation of the hierarchy.

Change-Id: Idc079feb3ca5f92d8bf337ef09efad006e267088
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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build(encrypt-fw): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ida53

build(encrypt-fw): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ida537d4c3e550f2fbbd977472ed6573491d17c23
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(cert-create): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ieda

build(cert-create): don't generate `build_msg.c`

This change avoids generating a build message source file on the shell,
instead using the `__DATE__` and `__TIME__` macros directly.

Change-Id: Ieda75bbac174847c716701bce8dd10b8e9975902
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "add_s32cc_clk_skeleton" into integration

* changes:
feat(s32g274a): use s32cc clock driver
feat(nxp-drivers): add clock skeleton for s32cc

Merge "fix(mhu): fix compilation error with ENABLE_ASSERTIONS=0 option" into integration

Merge "docs(fvp): update FVP versions used" into integration

fix(mhu): fix compilation error with ENABLE_ASSERTIONS=0 option

After disabling assertion with -DENABLE_ASSERTIONS=0, the build reports
error:

drivers/arm/mhu/mhu_wrapper_v3_x.c: In function 'mhu_g

fix(mhu): fix compilation error with ENABLE_ASSERTIONS=0 option

After disabling assertion with -DENABLE_ASSERTIONS=0, the build reports
error:

drivers/arm/mhu/mhu_wrapper_v3_x.c: In function 'mhu_get_max_message_size':
drivers/arm/mhu/mhu_wrapper_v3_x.c:448:31: error: variable 'err' set but not used [-Werror=unused-but-set-variable]
enum mhu_v3_x_error_t err;
^~~

This commit fixes the building failure by making the variable 'err' as
__maybe_unused.

Change-Id: I338e6df03d2f0805c83e96d8e3a4abae41e68678
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(s32g274a): use s32cc clock driver

To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.

Change-Id: I17ba195d8c3cf3f91

feat(s32g274a): use s32cc clock driver

To enable early clocks, such as A53, XBAR, and others, the clock driver
compilation should be included as part of the BL2 stage.

Change-Id: I17ba195d8c3cf3f91bd333a00d4a4af2f1f472b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b2

feat(nxp-drivers): add clock skeleton for s32cc

The S32CC is an umbrella for S32G2, S32G3 and S32R45 SoCs; therefore,
this clock driver will be used for all of these families.

Change-Id: Iede5371b212b67cf494a033c62fbfdcbe9b1a879
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "feat(cm): context switch MDCR_EL3 register" into integration

feat(st-reset): add stm32mp2_reset driver

This driver manages the resets of the peripherals embedded in STM32MP2.
Like clock driver, it also uses the RCC peripheral.

Change-Id: I8217891bdf1b847925a

feat(st-reset): add stm32mp2_reset driver

This driver manages the resets of the peripherals embedded in STM32MP2.
Like clock driver, it also uses the RCC peripheral.

Change-Id: I8217891bdf1b847925aad77f3f6ef542f08d1fba
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c689

feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

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Merge "fix(arm): string split into two lines causing error" into integration

fix(dt-bindings): update STM32MP2 clock and reset bindings

Fix some clocks and reset binding values.

Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.f

fix(dt-bindings): update STM32MP2 clock and reset bindings

Fix some clocks and reset binding values.

Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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