Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch

Merge changes from topic "nrd3_support" into integration

* changes:
feat(rdfremont): add support for measured boot at BL1 and BL2
feat(arm): mock support for CCA NV ctr
feat(rdfremont): fetch attestation key and token from RSE
feat(psa): introduce generic library for CCA attestation
feat(rdfremont): initialize the rse comms driver
feat(rdfremont): helper to initialize rse-comms with AP-RSE MHUv3
fix(rse): include lib-psa to resolve build
feat(neoverse-rd): add MHUv3 channels on third gen multichip platforms
feat(neoverse-rd): add MHUv3 doorbell channels on third gen platforms
feat(rdfremont): initialize GPT on GPC SMMU block
feat(rdfremont): update Root registers page offset for SMMUv3
feat(rdfremont): enable MTE2 if present on the platform
feat(rdfremont): enable SVE for SWD and NS
feat(rdfremont): enable AMU if present on the platform
feat(rdfremont): enable MPAM if present on the platform
feat(rdfremont): add DRAM pas entries in pas table for multichip
feat(rdfremont): add implementation for GPT setup
feat(rdfremont): integrate DTS files for RD-Fremont variants
feat(rdfremont): add support for RD-Fremont-Cfg2
feat(rdfremont): add support for RD-Fremont-Cfg1
feat(rdfremont): add support for RD-Fremont
feat(neoverse-rd): add scope for RD-Fremont variants
feat(neoverse-rd): add multichip pas entries
feat(neoverse-rd): add pas definitions for third gen platforms
feat(neoverse-rd): add DRAM layout for third gen platforms
feat(neoverse-rd): add SRAM layout for third gen platforms
feat(neoverse-rd): add firmware definitions for third gen platforms
feat(neoverse-rd): add RoS definitions for third gen platforms
feat(neoverse-rd): add CSS definitions for third gen platforms

show more ...

refactor(st): rename plat_set_image_source

The function is only used in this file and is static, no need to have
plat_ prefix. And as it is used only in case of FWU, when looking in
metadata, add it

refactor(st): rename plat_set_image_source

The function is only used in this file and is static, no need to have
plat_ prefix. And as it is used only in case of FWU, when looking in
metadata, add it in the function name.

Suggested-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I925c9c517216cf93bd74308c280c0f22c7734490

show more ...

docs: update Cortex-A32 FVP model version

Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297

S

docs: update Cortex-A32 FVP model version

Change [1] migrated Cortex-A32 FVP model to the default version used in
the TF-A CI.

[1] https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/29297

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I038087af957d3ee2b289944b4af1a8cffb1ec5ff

show more ...

fix(docs): replace "ARM-TF" with "TF-A" in diagrams

Two diagrams in the documentation contained the string "ARM TF", which
is probably a remainder of the older "ARM Trusted Firmware" name.
Replace t

fix(docs): replace "ARM-TF" with "TF-A" in diagrams

Two diagrams in the documentation contained the string "ARM TF", which
is probably a remainder of the older "ARM Trusted Firmware" name.
Replace that with "TF-A", which is now the more widely known name for
Trusted Firmware.
This was done with an image editing program, by just moving the letters
around, as I didn't find any source for that image.

Change-Id: I1fa18341b3aa8fc8c4ecc8988bf4de66e473caa7
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

fix(tc): add SCP_BL2 to RSE measured boot

SCP_BL2 is part of CCA's TCB. The SCP_BL1 is loaded
by RSE. It has already added to the platform
attestation token. SCP_BL2 was missed, so it is
fixed now.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic87743564136f03a901c90ff1ec614f5965b9a47

show more ...

Merge "fix(plat/marvell/a3k): reset GIC before resetting via CM3 secure coprocessor" into integration

Merge "refactor(qemu): use the example CCA platform token from iat-verifier" into integration

feat(st): add FWU with boot from NAND

Add the NAND use case in FWU boot. Like the NOR, NAND FWU won't use
a real partition UUID to find the correct FIP, but the UUID from
metadata will correspond wi

feat(st): add FWU with boot from NAND

Add the NAND use case in FWU boot. Like the NOR, NAND FWU won't use
a real partition UUID to find the correct FIP, but the UUID from
metadata will correspond with a hardcoded offset in the NAND.
Implement the plat_try_next_boot_source to load
backup partition on specific device.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I1dc544c479743d0ca2aace6e8214813d75637f50

show more ...

feat(st): manage backup partitions for NAND devices

Register a try_nand_backup_partitions() handler to plat_try_images_ops
to manage backup partition when booting from NAND devices.

Signed-off-by:

feat(st): manage backup partitions for NAND devices

Register a try_nand_backup_partitions() handler to plat_try_images_ops
to manage backup partition when booting from NAND devices.

Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ibee082b7b059b9e2ed502b7bbcda7464e5d9e251

show more ...

feat(bl): add plat handler for image loading

In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD device

feat(bl): add plat handler for image loading

In case of load error, platform may need to try another instance, either
from another storage, or from the same storage in case of PSA FWU. On
MTD devices such as NAND, it is required to define backup partitions.
A new function plat_setup_try_img_ops() should be called by platform
code to register handlers (plat_try_images_ops) to manage loading
other images.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: Ideaecaf296c0037a26fb4e6680f33e507111378a

show more ...

refactor(bl)!: remove unused plat_try_next_boot_source

The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.

refactor(bl)!: remove unused plat_try_next_boot_source

The plat_try_next_boot_source() API is not used by any upstream platform
and not used by platforms that asked for this API. It is then removed.
It will be replaced with a more generic interface in next patch.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I298c7acace8c5efb3c66422d8d9280ecd08e5ade

show more ...

fix(spm-mm): carve out NS buffer TZC400 region

SPM-MM defines AP TZC-400 regions as such:

1: 0xff000000 0xffffffff S
2: 0x80000000 0xfeffffff NS
3: 0x880000000 0xfffffffff NS
4: 0xff600000

fix(spm-mm): carve out NS buffer TZC400 region

SPM-MM defines AP TZC-400 regions as such:

1: 0xff000000 0xffffffff S
2: 0x80000000 0xfeffffff NS
3: 0x880000000 0xfffffffff NS
4: 0xff600000 0xff60ffff NS

Region 4 (using filter 0) defines the SPM NS shared buffer between
normal world and secure world.
However region 4 overlaps with region 1 (using filter 0) defined as
secure.
It is forbidden to define overlapping regions beyond region 0 for the
same filter. This is reported as a violation in the TZC-400 controller.

With FVP models < 11.25 the error is latent but not reported to the PE
(reason for this behavior is unclear).
With greater FVP model version the error is reported as an asynchronous
external abort (SError exception).

By carving out the SPM NS shared region (with regions as defined below),
the violation is no longer reported and test passed with recent FVP
models:

1: 0x80000000 0xfeffffff NS
2: 0xff000000 0xff5fffff S
3: 0xff600000 0xff60ffff NS
4: 0xff610000 0xffffffff S
5: 0x880000000 0xfffffffff NS

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idc3370803ad204ac29efeded77305e52e17cc1c1

show more ...

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB suppo

Merge changes from topic "dualroot_dtb" into integration

* changes:
refactor(fvp): add CoT desc dtsi
feat(arm): add COT_DESC_IN_DTB option for Dualroot
feat(fvp): add Dualroot CoT in DTB support
feat(dt-bindings): introduce Dualroot CoT DTB

show more ...

feat(st-clock): use early traces

Replace trace macros with their corresponding EARLY_* macros.

Change-Id: I39b163964fa3129be38e58352b5dee9b4081675b
Signed-off-by: Yann Gautier <yann.gautier@foss.st

feat(st-clock): use early traces

Replace trace macros with their corresponding EARLY_* macros.

Change-Id: I39b163964fa3129be38e58352b5dee9b4081675b
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

show more ...

fix(st-clock): adapt order of CSS on LSE and HSE

Fix the activation order of the CSS to prevent a faulty halt, according
to the reference manual (RM0442 Rev 6, Chapter: 10.4.3 Clock security
system

fix(st-clock): adapt order of CSS on LSE and HSE

Fix the activation order of the CSS to prevent a faulty halt, according
to the reference manual (RM0442 Rev 6, Chapter: 10.4.3 Clock security
system CSS) it must be done after selecting the LSE clock via the RTCSRC
field.
For the HSE clock, this can be activated even when HSEON is '0'.

Signed-off-by: Christoph Fritz <chf@fritzc.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ied01baac1ccc63dcef78bf5f9180bb8628cce2d0

show more ...

refactor(st-clock): remove unused struct

The struct clk_fixed_rate is used nowhere in the code, remove its
definition.

Change-Id: I139ad05a249357da96a996feabd4b1f53e290f2a
Signed-off-by: Yann Gauti

refactor(st-clock): remove unused struct

The struct clk_fixed_rate is used nowhere in the code, remove its
definition.

Change-Id: I139ad05a249357da96a996feabd4b1f53e290f2a
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

show more ...

feat(stm32mp1-fdts): remove RTC clock configuration

RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will

feat(stm32mp1-fdts): remove RTC clock configuration

RTC clock configuration is done now in OPTEE.
Note: The RTC clock source can only be configured once.
TF-A, configuring the RTC clock source will have no effect in OPTEE.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I111ba96b27d0de0c45086ba8ef947dd2e6785672

show more ...

refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock

Those functions are only used on MP1, they should not be in STM32 clock
core. Move them to MP13 driver (they are already in MP15 driver).
Redefin

refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock

Those functions are only used on MP1, they should not be in STM32 clock
core. Move them to MP13 driver (they are already in MP15 driver).
Redefine new clk_stm32_rcc_regs_*lock() functions in clock core. This
change avoid sparse warning:
drivers/st/clk/clk-stm32-core.c:46:6: warning: symbol
'stm32mp1_clk_rcc_regs_lock' was not declared. Should it be static?
drivers/st/clk/clk-stm32-core.c:51:6: warning: symbol
'stm32mp1_clk_rcc_regs_unlock' was not declared. Should it be static?

Change-Id: I9f255acaa843e41fc14267c1a8091f93bd029796
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

show more ...

refactor(st-clock): driver size optimization

Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and mini

refactor(st-clock): driver size optimization

Re-ordering structures to avoid gaps and minimize data.
Reduce type of gate_refcounts[], uint8_t is enough.
Re-ordering structures to avoid gaps and minimize data.
Use an unsigned char to define a clock ops type.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: I6b793dc34abdd6ef013609fc0f122da5d1824a34

show more ...

refactor(st-clock): remove BL32 support on STM32MP13

TF-A BL32 (SP_MIN) is not supported on STM32MP13. Only OP-TEE is used
as BL32. Remove the code under IMAGE_BL32 flag in STM32MP13 driver.

Signed

refactor(st-clock): remove BL32 support on STM32MP13

TF-A BL32 (SP_MIN) is not supported on STM32MP13. Only OP-TEE is used
as BL32. Remove the code under IMAGE_BL32 flag in STM32MP13 driver.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6cc9f230782c44129b205e66a44cdb4bcb5f95c3

show more ...

feat(st-clock): don't gate/ungate an oscillator if it is not wired

If the oscillator is not present, the gating will fail.

Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabrie

feat(st-clock): don't gate/ungate an oscillator if it is not wired

If the oscillator is not present, the gating will fail.

Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

show more ...

feat(dt-bindings): add missing SPIx bus clocks

Add SPI1, SPI2, SPI3, SPI4, SPI5 bus clocks.

Change-Id: I075447adc63944cdd97862f836c22e4210bdb047
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@

feat(dt-bindings): add missing SPIx bus clocks

Add SPI1, SPI2, SPI3, SPI4, SPI5 bus clocks.

Change-Id: I075447adc63944cdd97862f836c22e4210bdb047
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

show more ...

feat(stm32mp1-fdts): remove PLL1 settings

TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.

Change-Id: I0003337d8d37d

feat(stm32mp1-fdts): remove PLL1 settings

TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.

Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

show more ...

feat(st-clock): update with new bindings

Code alignment with MP13 driver.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ifb0597721a865f463cf41c5cd7be3ca75a1da80c

feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1

RCC bindings alignment with MP13 RCC bindings

Change-Id: I02c89accd51e4214cd009d4a9433d8d9b6aeba25
Signed-off-by: Gabriel Fernandez <gabriel.fe

feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1

RCC bindings alignment with MP13 RCC bindings

Change-Id: I02c89accd51e4214cd009d4a9433d8d9b6aeba25
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

show more ...