Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions fo

Merge changes from topic "st-nand-backup-fwu" into integration

* changes:
refactor(st): rename plat_set_image_source
feat(st): add FWU with boot from NAND
feat(st): manage backup partitions for NAND devices
feat(bl): add plat handler for image loading
refactor(bl)!: remove unused plat_try_next_boot_source

show more ...

refactor(docs): update RSE docs to match the example CCA token

The RSE documentation includes binary and JSON dumps of the CCA platform
token. This change updates those to match the example CCA pla

refactor(docs): update RSE docs to match the example CCA token

The RSE documentation includes binary and JSON dumps of the CCA platform
token. This change updates those to match the example CCA platform
token from [1], which is also the one returned by the TC and QEMU
platforms.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I21048e7f995eb24212cf62fb2128b576bc11ecff
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

show more ...

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software componen

refactor(tc): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in the Total Compute
platform.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I792e693cc994fc1e856f713fd97bac4930b28e1e
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

show more ...

Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove

Merge changes from topic "st_gpio_update" into integration

* changes:
fix(st-gpio): configure each GPIO mux as secure for STM32MP2
feat(st-gpio): add set GPIO config API
fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value
refactor(st): use GPIO banks definition from bindings
feat(dt-bindings): describe ST GPIO banks and config

show more ...

Merge "fix(tc): add SCP_BL2 to RSE measured boot" into integration

fix(st-gpio): configure each GPIO mux as secure for STM32MP2

GPIOs are configured as secure by default on STM32MP2. The former code
is then put under #if STM32MP13 || STM32MP15. The else part is for

fix(st-gpio): configure each GPIO mux as secure for STM32MP2

GPIOs are configured as secure by default on STM32MP2. The former code
is then put under #if STM32MP13 || STM32MP15. The else part is for
STM32MP2 family.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Change-Id: I80c5944d4ae662f9e28269c3dc543b13f0e26a7b

show more ...

feat(st-gpio): add set GPIO config API

Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.

Change-Id: I5e3acb5c95cd03f3e

feat(st-gpio): add set GPIO config API

Add get and set GPIO level from bank and pin value.
Add functions to set a pad in GPIO configuration
and to apply some settings.

Change-Id: I5e3acb5c95cd03f3e130e1a263b221b956cb3c8d
Signed-off-by: Pascal Paillet <p.paillet@st.com>

show more ...

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have

fix(stm32mp1): remove unnecessary assert on GPIO_BANK_A value

Remove assert for unexpected value of the define GPIO_BANK_A.

This check is not required as GPIO_BANK_A = 0, it can be limited to
have bank <= GPIO_BANK_K as bank is unsigned int.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I0345d56f106fcacd6a6f93281c2d9279980cd152

show more ...

refactor(st): use GPIO banks definition from bindings

Use GPIO banks definition from bindings.

Change-Id: I4dcf321345e319af78285e940b72a1369569b996
Signed-off-by: Pascal Paillet <p.paillet@st.com>

feat(dt-bindings): describe ST GPIO banks and config

Describe GPIO banks configs so that it can be used in
an STM32MP device-tree file.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I

feat(dt-bindings): describe ST GPIO banks and config

Describe GPIO banks configs so that it can be used in
an STM32MP device-tree file.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: If5dd05aae314cbb3189eb02c9fe555b832ac2bdb

show more ...

Merge changes from topic "ck/tf-a/verbosity-cleanup" into integration

* changes:
build: unify verbosity handling
build: add facilities for interpreting boolean values
build: add string casing

Merge changes from topic "ck/tf-a/verbosity-cleanup" into integration

* changes:
build: unify verbosity handling
build: add facilities for interpreting boolean values
build: add string casing facilities to utilities

show more ...

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 G

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.

Fix two more comments in qemu_pas_def.h since we're here.

Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

show more ...

fix(rockchip): add parenthesis for BITS_SHIFT macro

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ideac271469f0753c5b7aaed7bb07a792b64ae01e

fix(rockchip): xlat: fix compatibility between v1 and v2

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I1194ef232947ba90fa374466773373762a5acdb5

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from

feat(fvp): add cpu power control

Most newer CPU's have DSU and CPU power control core-off bit which
means before turning off CPUs from base power controller we need to
turn individual cores off from CPU Power control.

However there are certain older CPU's that don't have DSU and
don't support CPUPWRCTRL_EL1, so populate them as a list
and ignore setting core-off bit for those older CPU's as all newer
CPU's have them.

Note: unfortunately there is no mechanism to identify if a DSU is
present and CPUPWRCTRL_EL1 is supported through any CPU control
registers and CPUPWRCTRL_EL1 is supported only for ARM64 platforms
and not available in ARM32 platforms.

Change-Id: Iba6c3c8db60dbeb177cead7ebc65df8265860da7
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

refactor(cm): update SCTLR_EL2 initialisation

Currently, during the initial bootup phase SCTLR_EL2 register
has been initialised with the endianness bit based on header
attribute evaluation at EL3.

refactor(cm): update SCTLR_EL2 initialisation

Currently, during the initial bootup phase SCTLR_EL2 register
has been initialised with the endianness bit based on header
attribute evaluation at EL3.

This is not mandatorily required as TF-A by default, expects
the software at EL2 to execute in little endian format ( EE = 0).

Henceforth, this patch removes the endianness bit evaluation for
SCTLR_EL2 register and initialises with a predefined RESET value,
setting SCTLR_EL2.EE=0.

Change-Id: I53fdd5bf907cbe35c551fc03cc893821229ff807
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

show more ...

Merge "fix(spm-mm): carve out NS buffer TZC400 region" into integration

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables

build: unify verbosity handling

This change introduces a few helper variables for dealing with verbose
and silent build modes: `silent`, `verbose`, `q` and `s`.

The `silent` and `verbose` variables are boolean values determining
whether the build system has been configured to run silently or
verbosely respectively (i.e. with `--silent` or `V=1`).

These two modes cannot be used together - if `silent` is truthy then
`verbose` is always falsy. As such:

make --silent V=1

... results in a silent build.

In addition to these boolean variables, we also introduce two new
variables - `s` and `q` - for use in rule recipes to conditionally
suppress the output of commands.

When building silently, `s` expands to a value which disables the
command that follows, and `q` expands to a value which supppresses
echoing of the command:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed but not echoed'

When building verbosely, `s` expands to a value which disables the
command that follows, and `q` expands to nothing:

$(s)echo 'This command is neither echoed nor executed'
$(q)echo 'This command is executed and echoed'

In all other cases, both `s` and `q` expand to a value which suppresses
echoing of the command that follows:

$(s)echo 'This command is executed but not echoed'
$(q)echo 'This command is executed but not echoed'

The `s` variable is predominantly useful for `echo` commands, where you
always want to suppress echoing of the command itself, whilst `q` is
more useful for all other commands.

Change-Id: I8d8ff6ed714d3cb401946c52955887ed7dca602b
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

build: add facilities for interpreting boolean values

This is another small addition to the build system utlities to make it
easier to determine the truthiness of an arbitrary value.

This change ad

build: add facilities for interpreting boolean values

This is another small addition to the build system utlities to make it
easier to determine the truthiness of an arbitrary value.

This change adds the `bool` function, which takes a value and determines
whether the value is "truthy". We consider a value to be truthy if it is
NOT one of: "0", "n", "no", "f" or "false" (all case-insensitive).

If the value is truthy then it is returned as-is. Otherwise, no value
is returned.

Change-Id: I19347f4c3ae00a6b448514a28cc2d9d06f683f25
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

build: add string casing facilities to utilities

This is a small modification to two existing functions in the build
system: `uppercase` and `lowercase`.

These functions have been moved to the comm

build: add string casing facilities to utilities

This is a small modification to two existing functions in the build
system: `uppercase` and `lowercase`.

These functions have been moved to the common utilities makefile, and
use the `tr` tool to simplify their implementation. Behaviour is, for
virtually all use-cases, identical.

Change-Id: I0e459d92e454087e4188b2fa5968244e5db89906
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

Merge "docs: update Cortex-A32 FVP model version" into integration

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct

Merge changes from topic "st_clk_update" into integration

* changes:
feat(st-clock): use early traces
fix(st-clock): adapt order of CSS on LSE and HSE
refactor(st-clock): remove unused struct
feat(stm32mp1-fdts): remove RTC clock configuration
refactor(st-clock): move stm32mp1_clk_rcc_regs_*lock
refactor(st-clock): driver size optimization
refactor(st-clock): remove BL32 support on STM32MP13
feat(st-clock): don't gate/ungate an oscillator if it is not wired
feat(dt-bindings): add missing SPIx bus clocks
feat(stm32mp1-fdts): remove PLL1 settings
feat(st-clock): update with new bindings
feat(stm32mp1-fdts): new RCC DT bindings for STM32MP1
feat(dt-bindings): new RCC DT bindings
feat(stm32mp1): always boot at 650MHz
refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13
fix(st-clock): display proper PLL number for STM32MP13
fix(st-clock): do not reconfigure LSE
feat(stm32mp1-fdts): move RNG1 to CSI to improve random generation
refactor(st-clock): remove unused clk function in API
refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config
feat(st-clock): add function to restore generic timer rate

show more ...

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure acces

Merge changes from topic "us_mcn" into integration

* changes:
feat(tc): configure MCN rdalloc and wralloc mode
feat(tc): add dts entries for MCN PMU nodes
feat(tc): enable MCN non-secure access to pmu counters on TC3

show more ...

Merge "fix(docs): replace "ARM-TF" with "TF-A" in diagrams" into integration

refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core execut

refactor(dice): save parent context handle

Improve the restart handling of DPE. In the case of a restart
scenario where only that core is restarted which executes
the DPE client, but the core executes the DPE service
remains up and running. In this case, client needs to save
a valid context handle to be able to send commands again
to the DPE service during the new boot sequence.

BL1 saves a valid parent context handle to SDS
before passing the execution to BL2. This handle
can be used in case of a restart scenario when AP
is restarted but RSE is not. Because in that case
RSE does not save an initial context handle to SDS,
which meant to be used by AP during the boot process.

By then the very first initial context handle is
invalidated because it was already used in the
previous boot cycle by BL1.

BL2 does not need to do this, because the cold
boot starts with BL1.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Id14eefd2ec758f89f672af176e4f5386a397fa35

show more ...