build: consolidate directory creation rules

This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.

We cur

build: consolidate directory creation rules

This commit streamlines directory creation by introducing a single
pattern rule to automatically make directories for which there is a
dependency.

We currently use several macros to generate rules to create directories
upon dependence, which is a significant amount of code and a lot of
redundancy. The rule introduced by this change represents a catch-all:
any rule dependency on a path ending in a forward slash is automatically
created.

Now, rules can rely on an unordered dependency (`|`) on `$$(@D)/` which,
when secondary expansion is enabled, expands to the directory of the
target being built, e.g.:

build/main.o: main.c | $$(@D)/ # automatically creates `build/`

Change-Id: I7e554efa2ac850e779bb302fd9c7fbb239886c9f
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

Merge "refactor(cpus): modify log for "ERRATA_NOT_APPLIES"" into integration

fix(rmmd): remove the assert check for RMM_BASE

This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in

fix(rmmd): remove the assert check for RMM_BASE

This patch removes the assert from rmmd_setup() that checks if the
RMM image PC is equal to RMM_BASE. The RMM image can be relocated to
any address in the DRAM by the previous bootloader. So, providing the
RMM base address at compile time is not feasible for such platforms.

The assert check is now replaced with a runtime check for the RMM image.

Change-Id: I568cdb6f76f41d0dcdc7a95feb75e252a7c5c930
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

fix(std_svc): continue boot if rmmd_setup fails

This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the sce

fix(std_svc): continue boot if rmmd_setup fails

This patch allows the boot sequence to continue even if
rmmd_setup() fails. This allows platforms to use the same
RME-enabled image to support the scenarios where RMM image
is not present.

Change-Id: Ie4de15fb98ae7226eda410e15f1a650108dd8fb3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

fix(rmmd): ignore SMC FID when RMM image is not present

This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.

Change-Id

fix(rmmd): ignore SMC FID when RMM image is not present

This patch marks the RMM boot as failed, to ignore the SMC
FID for the RMM at runtime, if RMM image is not present on
the platform.

Change-Id: I3c19d886d32c56837a1a0d260d5204da8b2d12f1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

fix(rmmd): fail gracefully if RME is not enabled

This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the

fix(rmmd): fail gracefully if RME is not enabled

This patch converts the assert check for RME presence into
a runtime check and returns an error to fail gracefully. This
allows platforms to use the same image on boards that do not
support RME too.

Change-Id: I0cacdd7afd85ed3581e90ea81f0a51d076adb875
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

fix(rmmd): handle RMMD manifest loading failure

This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runt

fix(rmmd): handle RMMD manifest loading failure

This patch sets the rmm_boot_failed flag to true if the RMMD
manifest loading fails. This instructs the RMMD to ignore all
SMC FID for the RMM at runtime.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: If61be6200e28fcea7a5ad697393e83679f488abc

show more ...

feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b

feat(intel): enable VAB support for Intel products

This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.

Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Sig

feat(intel): add in SHA384 authentication

Add VAB SHA384 authentication implementation.

Change-Id: Ic22ab7416ffd0c514328d2815b136aa71ba96a84
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc

fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc7ff9b1f5d452641af11e576
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

Merge changes If8547b5a,I6826a56d,Idb40907a,Ia51cbe1a,I9b55f6c5, ... into integration

* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory

Merge changes If8547b5a,I6826a56d,Idb40907a,Ia51cbe1a,I9b55f6c5, ... into integration

* changes:
feat(fvp): add SPM manifest for OP-TEE at S-EL1 without S-EL2/Hafnium
fix(fvp): update the memory size allocated to optee at EL1
fix(fvp): add DRAM memory regions that linux kernel can share
feat(fvp): update FF-A version to v1.1 supported by optee
feat(fvp): replace managed-exit with ns-interrupts-action
fix(fvp): add optee specific mem-size attribute
fix(fvp): fix the FF-A optee manifest by adding the boot info node

show more ...

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id: I78d8ee0596c3e7bd4883bfd6e92c883b8e369c10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

Merge "fix(intel): f2sdram bridge quick write thru failed" into integration

Merge "feat(intel): add QSPI get devinfo mailbox cmd" into integration

Merge "fix(docs): fix CPU type for mt8195" into integration

refactor(cpus): modify log for "ERRATA_NOT_APPLIES"

modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.

Change-Id: I8f60636320f617

refactor(cpus): modify log for "ERRATA_NOT_APPLIES"

modify the print logs when an erratum workaround does not
need to be applied to a certain revision/variant of the CPU.

Change-Id: I8f60636320f617ecd4ed88ee1fbf7a3e3e4517ee
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

show more ...

Merge "fix(mt8188): remove BL32 region protection if SPD sets to none" into integration

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghenn

feat(nxp-clk): enable the A53 clock

Enable the A53 clock at 1GHz, the maximum frequency on S32G2 SoCs.

Change-Id: Ife96792faf8f3f46965bdcf4df75fcca5e39dc6e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2

feat(nxp-clk): add ARM PLL ODIV enablement

Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.

Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which

feat(nxp-clk): add ARM PLL enablement

Add the low-level implementation to enable the ARM PLL oscillator, which
is disabled by default when booting the SoC. It will be used by PLL
diviers, for which support will be added later.

Change-Id: I964fa7374ea9a08c695009176eade01003c1d6c2
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0

feat(nxp-clk): set rate for clock muxes

The clock muxes will simply pass the set rate request to the clock
module connected to its source, as they do not alter the frequency.

Change-Id: I5fda8fffa0f46a4be96deac4d6a5a880c9f86ccf
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

fix(mt8188): remove BL32 region protection if SPD sets to none

When SPD is set to none, it means we don't run any secure OS on the
system. We should make this memory region available to kernel.

Cha

fix(mt8188): remove BL32 region protection if SPD sets to none

When SPD is set to none, it means we don't run any secure OS on the
system. We should make this memory region available to kernel.

Change-Id: Ia83ff4a7d25de38a5d845b7ee1367bafed43bbdd
Signed-off-by: Yidi Lin <yidilin@chromium.org>

show more ...

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash

feat(fgt2): add support for FEAT_FGT2

This patch disables trapping to EL3 when the FEAT_FGT2
specific trap registers are accessed by setting the
SCR_EL3.FGTEn2 bit

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I6d2b614affb9067b2bc3d7bf0ae7d169d031592a

show more ...

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed

feat(debugv8p9): add support for FEAT_Debugv8p9

This patch enables FEAT_Debugv8p9 and prevents EL1/0 from
trapping to EL3 when accessing MDSELR_EL1 register by
setting the MDCR_EL3.EBWE bit.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3613af1dd8cb8c0d3c33dc959f170846c0b9695a

show more ...

Merge changes from topic "clk_fixed_divider" into integration

* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL di

Merge changes from topic "clk_fixed_divider" into integration

* changes:
feat(nxp-clk): set rate for clock fixed divider
feat(nxp-clk): add A53 clock objects
feat(nxp-clk): set rate for PLL divider objects
feat(nxp-clk): set rate for PLL objects

show more ...