Merge "build: fix missing `$$(@D)/` from `sp_gen.mk`" into integration

fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more spa

fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more space
in secure RAM for BL32 image, this patch removes NS_SHARED_RAM region
which is not currently used by corstone1000 platform.

Change-Id: I1e9468fd2dcb66b4d21fce245097ba51331ec54d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

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fix(corstone1000): pass spsr value explicitly

Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.

Change-Id: I06b5b75

fix(corstone1000): pass spsr value explicitly

Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.

Change-Id: I06b5b750f963f8609e00ff6bf2838bac0f8b7b28
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

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fix(arm): remove duplicate jumptable entry

Change-Id: I4cc4ef493318372ec0d0531ca3e98196e7065ab9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

build: fix missing `$$(@D)/` from `sp_gen.mk`

This target can currently fail as the `$(BUILD_PLAT)` target no longer exists, as it is now `$(BUILD_PLAT)/` (with an explicit trailing slash).

Change-

build: fix missing `$$(@D)/` from `sp_gen.mk`

This target can currently fail as the `$(BUILD_PLAT)` target no longer exists, as it is now `$(BUILD_PLAT)/` (with an explicit trailing slash).

Change-Id: I9172b2f51f6e02e6369f62468ea63a64ec0f6dd1
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: make poetry use existing lock file

This makes the build reproducible.

When `make dev-install` was run, it would ignore the existing
poetry lock file, install different versions of all the
li

build: make poetry use existing lock file

This makes the build reproducible.

When `make dev-install` was run, it would ignore the existing
poetry lock file, install different versions of all the
libraries, then overwrite the lock file. Once `--no-update`
is added, it stops doing that, and installs exactly what is
in the poetry lock file.

Change-Id: If62637a40504d23deb47a05347a272e1c13bf41e
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>

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feat(arm): add fw handoff support for RESET_TO_BL31

Change-Id: I78f3c5606f0221bb5fc613a973a7d3fe187db35b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

feat(tlc): add host tool for static TL generation

Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specific

feat(tlc): add host tool for static TL generation

Transfer List Compiler is a command line tool that enables the static
generation of TL's compliant with version 0.9 of the firmware handoff
specification. The intent of this tool is to support information passing
via the firmware handoff framework to bootloaders that run without
preceding images (i.e. `RESET_TO_BL31`).

It currently allows for TL's to be statically generated from blobs of
data, and modified by removing/adding TE's. Future work will provide
support for TL generation from configuration file.

Change-Id: Iff670842e34c9ad18eac935248ee2aece43dc533
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Co-authored-by: Charlie Bareham <charlie.bareham@arm.com>

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feat(trbe): introduce trbe_disable() function

This patch adds trbe_disable() which disables Trace buffer access
from lower ELs in all security state. This function makes Secure
state the owner of Tr

feat(trbe): introduce trbe_disable() function

This patch adds trbe_disable() which disables Trace buffer access
from lower ELs in all security state. This function makes Secure
state the owner of Trace buffer and access from EL2/EL1 generate
trap exceptions to EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: If3e3bd621684b3c28f44c3ed2fe3df30b143f8cd

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feat(spe): introduce spe_disable() function

Introduce a function to disable SPE feature for Non-secure state and do
the default setting of making Secure state the owner of profiling
buffers and trap

feat(spe): introduce spe_disable() function

Introduce a function to disable SPE feature for Non-secure state and do
the default setting of making Secure state the owner of profiling
buffers and trap access of profiling and profiling buffer control
registers from lower ELs to EL3.

This functionality is required to handle asymmetric cores where SPE has
to disabled at runtime.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2f99e922e8df06bfc900c153137aef7c9dcfd759

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chore(spe): rename spe_disable() to spe_stop()

During CPU power down, we stop the profiling by calling spe_disable()
function. From TF-A point of view, enable/disable means the avaibility
of the fea

chore(spe): rename spe_disable() to spe_stop()

During CPU power down, we stop the profiling by calling spe_disable()
function. From TF-A point of view, enable/disable means the avaibility
of the feature for lower EL. In this case we are not actully disabling
the feautre but stoping it before power down.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I6e3b39c5c35d330c51e7ac715446a8b36bf9531f

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Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SP

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

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Merge "build(amu): restrict counters (RAZ)" into integration

Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: ad

Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model

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Merge "feat(rcar3): populate kaslr-seed in next stage DT" into integration

Merge "fix(fvp): add secure uart interrupt in device region" into integration

Merge "build: consolidate directory creation rules" into integration

Merge "feat(fvp): add flash areas for secure partition" into integration

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.

Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>

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fix(fvp): add secure uart interrupt in device region

OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
De

fix(fvp): add secure uart interrupt in device region

OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
Define the UART interrupt in the FF-A device region node.
Without this change, OPTEE panics at the boot with the following:

| I/TC: No non-secure external DT
| I/TC: manifest DT found
| I/TC: OP-TEE version: 4.3.0-23-gfcd8750677db
| I/TC: WARNING: This OP-TEE configuration might be insecure!
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
| I/TC: Primary CPU initializing
| E/TC:0 0 assertion '!res' failed at core/drivers/hfic.c:56 <hfic_op_enable>
| E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>
| E/TC:0 0 TEE load address @ 0x6284000

Change-Id: Icddcdfd032315aeee65ba3100f3a6b470a74435d
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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Merge changes from topic "rmmd-graceful-exit" into integration

* changes:
fix(rmmd): remove the assert check for RMM_BASE
fix(std_svc): continue boot if rmmd_setup fails
fix(rmmd): ignore SMC

Merge changes from topic "rmmd-graceful-exit" into integration

* changes:
fix(rmmd): remove the assert check for RMM_BASE
fix(std_svc): continue boot if rmmd_setup fails
fix(rmmd): ignore SMC FID when RMM image is not present
fix(rmmd): fail gracefully if RME is not enabled
fix(rmmd): handle RMMD manifest loading failure

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refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory alloca

refactor(cm): convert el1-ctx assembly offset entries to c structure

Currently the EL1 part of the context structure (el1_sysregs_t),
is coupled with feature flags reducing the context memory allocation
for platforms, that don't enable/support all the architectural
features at once.

Similar to the el2 context optimization commit-"d6af234" this patch
further improves this section by converting the assembly context-offset
entries into a c structure. It relies on garbage collection of the
linker removing unreferenced structures from memory, as well as aiding
in readability and future maintenance. Additionally, it eliminates
the #ifs usage in 'context_mgmt.c' source file.

Change-Id: If6075931cec994bc89231241337eccc7042c5ede
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
rest

feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

* Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default
for few cores and they need context entries for saving and
restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times.

* This prevents the mechanism of decoupling EL1 and EL2 registers,
as EL3 firmware shouldn't be handling both simultaneously.

* Depending on the build configuration either EL1 or EL2 context
structures need to included, which would result in saving a good
amount of context memory.

* In order to achieve this it's essential to have explicit context
entries for registers supporting "ERRATA_SPECULATIVE_AT".

* This patch adds two context entries under "errata_speculative_at"
structure to assist this errata and thereby allows decoupling
EL1 and EL2 context structures.

Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and remove

refactor(cpus): remove cpu specific errata funcs

Errata printing is done directly via generic_errata_report.
This commit removes the unused \_cpu\()_errata_report
functions for all cores, and removes errata_func from cpu_ops.

Change-Id: I04fefbde5f0ff63b1f1cd17c864557a14070d68c
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(cpus): directly invoke errata reporter

In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic

refactor(cpus): directly invoke errata reporter

In all non-trivial cases the CPU specific errata functions
already call generic_errata_report, this cuts out the middleman
by directly calling generic_errata_report from
print_errata_status.

The CPU specific errata functions (cpu_ops->errata_func)
can now be removed from all cores, and this field can be
removed from cpu_ops.

Also removes the now unused old errata reporting
function and macros.

Change-Id: Ie4a4fd60429aca37cf434e79c0ce2992a5ff5d68
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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