feat(arm): generate tbbr c file CoT dt2c

Integrate the cot-dt2c tool into build process
for TBBR configuration

Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin

feat(arm): generate tbbr c file CoT dt2c

Integrate the cot-dt2c tool into build process
for TBBR configuration

Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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feat(arm): makefile invoke CoT dt2c

Change the makefile to call the cot-dt2c tool
during the build for Arm platform

Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0
Signed-off-by: Xialin Liu <X

feat(arm): makefile invoke CoT dt2c

Change the makefile to call the cot-dt2c tool
during the build for Arm platform

Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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feat(auth): standalone CoT dt2c tool

Add the standalone CoT dt2c tool for CoT DTB conversion to
c file

Change-Id: If28e580a4c2825f5dc9008e93cd2aae3fc173e73
Signed-off-by: Xialin Liu <Xialin.Liu@ARM

feat(auth): standalone CoT dt2c tool

Add the standalone CoT dt2c tool for CoT DTB conversion to
c file

Change-Id: If28e580a4c2825f5dc9008e93cd2aae3fc173e73
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(auth): separate bl1 and bl2 CoT

Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.

Change-Id: I0d24791991b3539c7

refactor(auth): separate bl1 and bl2 CoT

Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.

Change-Id: I0d24791991b3539c7aef9a562920dc62fecdc69a
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(st): align the NV counter naming

align the nv counter naming for stm32mp1-cot-descriptor.dtsi file

Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Li

refactor(st): align the NV counter naming

align the nv counter naming for stm32mp1-cot-descriptor.dtsi file

Change-Id: I8c41c5e323e8bf867e08b4590dfb42e86204ab65
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renamin

refactor(fvp): align the NV counter naming

Align the naming of nv_counter to nv_ctr in the DTBs
so that they match with the static C files. Update the
binding documentation accordingly. This renaming is beneficial
for the upcoming conversion tool that will convert CoT DT files
to C files.

Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
fea

Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
feat(nxp-clk): set rate for clock muxes

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fix(rdv3): remove NEED_* from RD-V3 makefile

As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.

Signed-off-by:

fix(rdv3): remove NEED_* from RD-V3 makefile

As the NEED_* are internal flags used in the build system and are not
meant to be used by platforms, remove them from the RD-V3 makefile.

Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com>
Change-Id: If7144b9d72c16e8025f929f2546abd96194615ce

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fix(poplar): shutdown wdt0 before powering off

Shut down watchdog0 before panic() to avoid the system being reset by
it.

Signed-off-by: Yang Xiwen <forbidden405@foxmail.com>
Change-Id: I4982202db92

fix(poplar): shutdown wdt0 before powering off

Shut down watchdog0 before panic() to avoid the system being reset by
it.

Signed-off-by: Yang Xiwen <forbidden405@foxmail.com>
Change-Id: I4982202db9252b42312bd5f0f6e0729024a157df

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Merge "fix(nxp-sfp): shift gpio register offsets by 2" into integration

fix(gicv3): incorrect impdef power down sequence

The GICR_WAKER.Sleep and GICR_WAKE.Quiescent functionality is solely
about flushing out the LPI cache and ensuring that the contents are
consistent w

fix(gicv3): incorrect impdef power down sequence

The GICR_WAKER.Sleep and GICR_WAKE.Quiescent functionality is solely
about flushing out the LPI cache and ensuring that the contents are
consistent with external memory.

Hence, as shown in GIC-700 TRM version r3p0, software must poll for
Quiescent bit only if LPIs are supported.

Change-Id: I7d69b208428e24d8a3ff30e81bd1a8ee3d0bda6e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "refactor(cpufeat): feat detect helpers inlining" into integration

Merge "fix(ast2700): fix mpll calculate statement" into integration

fix(psci): fix parent parsing in psci_is_last_cpu_to_idle_at_pwrlvl

The function always checks the first parent of the current core
instead parse the tree topology to find the parent at parent level

fix(psci): fix parent parsing in psci_is_last_cpu_to_idle_at_pwrlvl

The function always checks the first parent of the current core
instead parse the tree topology to find the parent at parent level
of the CPU. It is because the current loop has no effect as it uses
a fixed parameter 'my_idx' and returns the FIRST parent of CPU.
Also, it looks for the parent nodes in the array of CPU nodes, but
actually they are in a separate array.

This update allows to parse the PSCI topology tree to find
the parent at parent level of the CPU identified by my_idx.

Fixes: 606b7430077c ("feat(psci): add support for OS-initiated mode")
Change-Id: I96fb5ecc154a76b16adca5b5055217b8626c9e66
Signed-off-by: Charlie Bareham <charlie.bareham@arm.com>

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Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc):

Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc): change GIC DT property 'interrupt-cells' to 4
feat(tc): add NI-Tower PMU node for TC3
feat(tc): setup ni-tower non-secure access for TC3

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fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signe

fix(tc): correct CPU PMU binding

CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU nodes per micro architectures.

Change-Id: I4e940976cdda9a6eab3e15936c6c41a2bb668c9d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface

feat(tc): add device tree binding for SPE

Add node for Statistical Profiling Extension, which provides
periodic sampling of operations in the CPU pipeline and reports
this via the perf AUX interface.

Change-Id: Ic7a9d9ce927edbce02c7c09470a009dc56247240
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes fo

feat(tc): add PPI partitions in DT binding

Define ppi-partitions for little, middle, and big cpu groups. PPI
affinity is expressed as a single "ppi-partitions" node, containing a
set of sub-nodes for each microarchitecture type, each with the
property 'affinity' which should be a list of phandles to CPU nodes.

PPI paritions are useful to affine specific PPI with set of CPUs
so that the drivers of micro-architecture specific nodes which uses
PPI can be divided based on CPU list e.g. SPE-PMU, CPU-PMU etc.

Change-Id: If7d47f71387ac982d2d992a0ce2de1652d564bd6
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine

feat(tc): change GIC DT property 'interrupt-cells' to 4

Change the GIC's DT property 'interrupt-cells' to 4, so the 4th cell is
a phandle to a node describing a set of CPUs this interrupt is affine
to.

If an interrupt is a PPI, and the node pointed in the 4th cell must be a
subnode of the "ppi-partitions" in the GIC node. For interrupt types
other than PPI, this cell must be zero. This is a preparison for
sequential changes for interrupt partitions, as the first step, it sets
all zeros for the interrupt affinity.

Change-Id: I66490a86a27aad5db6b1a42c2d8e0d042eee46a9
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Ya

feat(tc): add NI-Tower PMU node for TC3

Enable NI-Tower PMU on TC3.

Change-Id: I8a4d4e31e84ab33f95bc8b7661e873cf97561b79
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): setup ni-tower non-secure access for TC3

NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.

Change-Id: I83a8b3a1d2778baf767ff932

feat(tc): setup ni-tower non-secure access for TC3

NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.

Change-Id: I83a8b3a1d2778baf767ff93263e246d127ef8114
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "ar/asymmetricSupport" into integration

* changes:
feat(trbe): introduce trbe_disable() function
feat(spe): introduce spe_disable() function
chore(spe): rename spe_dis

Merge changes from topic "ar/asymmetricSupport" into integration

* changes:
feat(trbe): introduce trbe_disable() function
feat(spe): introduce spe_disable() function
chore(spe): rename spe_disable() to spe_stop()

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Merge changes from topic "corstone1000-bugfixes" into integration

* changes:
fix(corstone1000): update memory layout comments
fix(corstone1000): clean cache and disable interrupt before system r

Merge changes from topic "corstone1000-bugfixes" into integration

* changes:
fix(corstone1000): update memory layout comments
fix(corstone1000): clean cache and disable interrupt before system reset
fix(corstone1000): remove unused NS_SHARED_RAM region
fix(corstone1000): pass spsr value explicitly

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Merge changes from topic "hm/handoff" into integration

* changes:
fix(arm): move HW_CONFIG relocation into BL31
feat: add option to input attr as string of flag names
feat: add option to input

Merge changes from topic "hm/handoff" into integration

* changes:
fix(arm): move HW_CONFIG relocation into BL31
feat: add option to input attr as string of flag names
feat: add option to input text instead of tag id number
feat: add creating transfer lists from yaml files

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Merge "fix(arm): correct the RESET_TO_BL31 x1 handoff arg" into integration