feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for

feat(arm): setup GPT in BL31 in RESET_TO_BL31 boot flow

In the normal boot flow, BL2 sets up the Granule Protection Tables
(GPT). As BL2 is not a part of RESET_TO_BL31, BL31 needs to set up GPT
for CPUs supporting FEAT_RME.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I9ad16bd93ea9fbad422dd56e2ba1d600a30eea30

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feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@a

feat(neoverse-rd): enable RESET_TO_BL31 for RD-V3

Update addresses for BL31, BL33 and NT_FW_CONFIG. Also add the PAS
entries to setup GPT tables in BL31.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I8947660bb96fdf2f178e560b387e4bc93bf68abf

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feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add supp

feat(neoverse-rd): add a routine to update NT_FW_CONFIG in BL31

In the BL1 based boot-flow, the non-secure DTB, NT_FW_CONFIG, is parsed
in BL2. As BL1 and BL2 are not part of RESET_TO_BL31, add support to
parse and configure this DTB in BL31. NT_FW_CONFIG contains the platform
information which is needed by BL33.

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: Ib1fb5417c36523eb2ec02aa22845218de68809aa

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fix(cpus): workaround for Cortex-X4 erratum 2897503

Cortex-X4 erratum 2897503 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.

The workaround is to set CPUACTLR4_EL1[8

fix(cpus): workaround for Cortex-X4 erratum 2897503

Cortex-X4 erratum 2897503 is a Cat B erratum that applies
to all revisions <= r0p1 and is fixed in r0p2.

The workaround is to set CPUACTLR4_EL1[8] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2432808/latest

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3178a890b6f1307b310e817af75f8fdfb8668cc9

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Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken

Merge changes from topic "nxp-drivers/add-get-parent-callback" into integration

* changes:
feat(nxp-clk): refactor clock enablement
feat(nxp-clk): add get_parent callback
fix(nxp-clk): broken UART clock initalization

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Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fd

Merge changes I14df5d21,I7f952205,I6f52ec2c,Ibe0cacf8 into integration

* changes:
feat(stm32mp2-fdts): describe stpmic2 power supplies
feat(stm32mp2-fdts): add I2C7 pin muxing
feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2
feat(st-pmic): add STPMIC2 driver

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Merge "feat(stm32mp2): improve BL31 size management" into integration

Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix s

Merge changes from topic "hm/tlc" into integration

* changes:
feat(handoff): make tl generation flexible
feat(tlc): add command gen-header
feat(tlc): add support for tox
refactor(tlc): fix static check errors and code style

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Merge "fix(intel): add cache invalidation during BL31 initialization" into integration

fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the

fix(intel): add cache invalidation during BL31 initialization

During warm boot, the data cache is invalidated before
enabling them in u-boot proper, this cache
invalidation (+ cleaning) leads to the sync-up of stale
values in the cache to be synced with the main memory.
So, before the cache cleaning is done in u-boot proper,
it is invalidated in BL31 so that the cache data gets in
sync with u-boot proper memory address space and when
u-boot proper does its initialization which in turn clears
its BSS and heap section.

Change-Id: Ic8d8672f1e371868be7f54f5a1fae9229ab15164
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): bridge ack timing issue causing fpga config hung" into integration

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signe

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "docs: update TF-A Nov'24 release dates" into integration

Merge changes from topic "update-mbedtls-to-3.6.1" into integration

* changes:
refactor(mbedtls): remove hack in LIBMBEDTLS_CFLAGS
docs(prerequisites): update MbedTLS version to 3.6.1

Merge "feat(rk3588): enable crypto function" into integration

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxim

feat(stm32mp2): improve BL31 size management

Change the size of BL31 limit allocation to be half the sysram size.
Defining BL31_PROGBITS_LIMIT to detect overflows.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iccc1cc0826b8113a3c2fd6ffa77ca419795854d3

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Merge "fix(rpi3): manually populate CNTFRQ reg" into integration

fix(st): support device tree DDR sizes higher than 16Gbits for aarch64

In that case, memory address space is higher than 4GB, so 32-bits
addressing is not enough.
Get st,mem-size property value on 6

fix(st): support device tree DDR sizes higher than 16Gbits for aarch64

In that case, memory address space is higher than 4GB, so 32-bits
addressing is not enough.
Get st,mem-size property value on 64bits (size_t type in structures).

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I1df23bfa7a850fc3f5a4ef9fc5d2f76ab6c6dea8

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feat(fdt-wrappers): add function to read uint64 with default value

Adds a new utility function fdt_read_uint64_default() to read a uint64
value with a default value, as it is already done for uint32

feat(fdt-wrappers): add function to read uint64 with default value

Adds a new utility function fdt_read_uint64_default() to read a uint64
value with a default value, as it is already done for uint32.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibc85e30c3e4dd4b5171bdec106f4e32eb78c579f

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fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from e

fix(el3-spmc): use write_el1_ctx_timer() macro to set cntkctl_el1 value

commit 42e35d2f8c0e
("refactor(cm): convert el1 ctx assembly offset entries to c structure")
moves cntkctl_el1 register from el1_sysregs_t's common to arch_timer
structure.
To set cntkctl_el1, it should use write_el1_ctx_timer() instead of
write_el1_ctx_common() otherwise, build failed.

Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ifa1ca6e056fa95bd07598d20705856e208670808

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feat(stm32mp2-fdts): describe stpmic2 power supplies

Describe PMIC power supplies in STM32MP257F-EV1 board DT file.

Change-Id: I14df5d210909d95b2164197eb910a9ea0aa0b51d
Signed-off-by: Pascal Paille

feat(stm32mp2-fdts): describe stpmic2 power supplies

Describe PMIC power supplies in STM32MP257F-EV1 board DT file.

Change-Id: I14df5d210909d95b2164197eb910a9ea0aa0b51d
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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feat(stm32mp2-fdts): add I2C7 pin muxing

It will be used for PMIC on STM32MP257F-EV board.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7f95220512de4416323b381fec7c7dcb044c64fd

feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2

Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxi

feat(stm32mp2-fdts): add UART and I2C nodes for STM32MP2

Update stm32mp251.dtsi SoC DT file to include UART and I2C nodes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I6f52ec2c1735d28ba4a424af71e7eae5b0ac3e0d

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feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boo

feat(st-pmic): add STPMIC2 driver

The STPMIC2 embeds 15 regulators with various
properties, and is designed to supply the STM32MP2
SOC. This driver handles a minimal set of feature
to handle the boot of a board.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibe0cacf8aec2871eb9a86ec16cbbd18d3745fe9e

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Merge changes Idf032b03,Id8e803b3 into integration

* changes:
feat(st-regulator): support regulator_set_voltage for fixed regulator
feat(st-regulator): add enable ramp-delay