History log of /rk3399_ARM-atf/ (Results 2876 – 2900 of 18314)
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00a6842707-Mar-2024 Prasad Kummari <prasad.kummari@amd.com>

chore(xilinx): rename runtime console to DT console

Renames the runtime_console_init() function to dt_console_init()
for better naming clarity.

Change-Id: I7f6d80ce23307d57e09c613be48482d49d6ad45b

chore(xilinx): rename runtime console to DT console

Renames the runtime_console_init() function to dt_console_init()
for better naming clarity.

Change-Id: I7f6d80ce23307d57e09c613be48482d49d6ad45b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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569a03c707-May-2024 Jit Loon Lim <jit.loon.lim@intel.com>

fix(intel): update mailbox SDM printout message

The printout message is misleading.
Update the message content and mask out the return code.

Change-Id: I08acb73894f8504b2773a19dbb10b42a65fcda5d
Sig

fix(intel): update mailbox SDM printout message

The printout message is misleading.
Update the message content and mask out the return code.

Change-Id: I08acb73894f8504b2773a19dbb10b42a65fcda5d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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5d38dc0902-Oct-2024 Mark Dykes <mark.dykes@arm.com>

Merge "fix(intel): update CCU configuration for Agilex5 platform" into integration

d7890a5f02-Oct-2024 André Przywara <andre.przywara@arm.com>

Merge "feat(build): add ability to define platform specific defaults" into integration

d596023b08-Mar-2022 Nicolas Le Bayon <nicolas.le.bayon@st.com>

refactor(st-ddr): create generic services

Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Fa

refactor(st-ddr): create generic services

Disabling AXI port, enabling host interface and both enabling/disabling
software self-refresh services are already present inside the driver
source code.
Factorize by gathering them as services inside the generic part,
and adapt driver to call these new functions.

Add services to manage quasi-dynamic registers. DDRCTRL contains
quasi-dynamic registers, which are dynamic only under some conditions
defined by the user guide (with 4 groups).
In our driver, out of reset state, only groups 3 and 4 are updated.
Group 4 needs only sw_done/sw_done_ack sequence, already available.
Group 3 sequence include more conditions, that are gathered in
specific services. stm32mp_ddr_disable_host_interface() has been added
to do this.

Add dedicated generic service to toggle rfshctl3.refresh_update_level
and wait for completion.

Manage AXI ports and HIF when updating QD3 registers. Quasi-dynamic
group 3 (QD3) registers are updated when DDR is not completely
initialized, i.e. when AXI ports are not enabled and possibly when
host interface (HIF) is not enabled too.
In that case, a specific mechanism is necessary to restore the same
conditions as before accessing QD3 registers.
Static functions have been added to get AXI ports and HIF states and
are used to determine the needed conditions to set/unset.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I880f88b1cb6fc76199ad9ea33e9d63a5c469aed4

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1483b3c329-May-2024 Yann Gautier <yann.gautier@st.com>

refactor(st-ddr): remove name from stm32mp_ddr_reg_desc

It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.

Signed-off-by: Yann Gautier <ya

refactor(st-ddr): remove name from stm32mp_ddr_reg_desc

It was only used for an error trace, with little added value. This
allows some gains in DDR driver data size.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I02e2fc75efd90ff188e62f39850b9bd4c3af1649

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066a595829-May-2024 Yann Gautier <yann.gautier@st.com>

refactor(st-ddr): add definition for timeouts and delays

Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.

Signed-

refactor(st-ddr): add definition for timeouts and delays

Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I489084132821774b0049a4a5d7fc30db24a7bb11

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87cd847c24-Nov-2021 Yann Gautier <yann.gautier@st.com>

feat(st): add stm32mp_is_wakeup_from_standby()

This function is used to know if this is a return from Standby mode,
and the DDR was in self-refresh, allowing a correct return to OS.
They just return

feat(st): add stm32mp_is_wakeup_from_standby()

This function is used to know if this is a return from Standby mode,
and the DDR was in self-refresh, allowing a correct return to OS.
They just return false for the moment.

Change-Id: Ie7de9a9f6477f8158e144f6626070a77fdc53ceb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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52f530d319-Sep-2024 Maxime Méré <maxime.mere@foss.st.com>

feat(stm32mp2): add RETRAM map/unmap capability

Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in

feat(stm32mp2): add RETRAM map/unmap capability

Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in order to restore them in standby exit sequence.
Add map/unmap services at platform level and configure dedicated RISAB5.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I460b36fccce62e83c1fbff298f96b23530aaa4f3

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2fd7b23021-Sep-2021 Nicolas Le Bayon <nicolas.le.bayon@st.com>

feat(stm32mp2): add helper to get DDRDBG base address

Add a function to get DDRDBG peripheral IO memory base address.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I20d14fca4

feat(stm32mp2): add helper to get DDRDBG base address

Add a function to get DDRDBG peripheral IO memory base address.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I20d14fca49528c296c1f7d49a66129d932f44e49

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e2d6e5e218-Jan-2023 Pascal Paillet <p.paillet@st.com>

feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad

feat(stm32mp2): handle DDR power supplies

Modify platform driver to handle the DDR power supplies when
a PMIC is present.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I98df132a63c2ad351d4dae949f5dbb831cc40637

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47e6231416-Feb-2023 Patrick Delaunay <patrick.delaunay@foss.st.com>

feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

feat(stm32mp1): handle DDR power supplies

Modify the DDR driver to handle the DDR power supplies when a PMIC
is present in the function stm32mp_board_ddr_power_init(), define
in the platform file.

This patch allows to easily modify the used DDR power supplies
for customer boards, when they don't use STPMIC1 PMU or when
the regulators are not connected as on the STMicroelectronics
boards.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I93ee6295ef7032ac20f03608d22cd460f7d87ef5

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1f6cf1e401-Oct-2024 Olivier Deprez <olivier.deprez@arm.com>

Merge "refactor: digest sizes" into integration

cc3d73cc01-Oct-2024 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default

Merge changes I1df23bfa,Ibc85e30c into integration

* changes:
fix(st): support device tree DDR sizes higher than 16Gbits for aarch64
feat(fdt-wrappers): add function to read uint64 with default value

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26467bf301-Oct-2024 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL

Merge changes from topic "rd1ae-upstream" into integration

* changes:
docs(rd1ae): add RD-1 AE documentation
feat(rd1ae): enabling Trusted Board Boot(TBB) for RD-1 AE
feat(rd1ae): introduce BL31 for RD-1 AE platform
feat(rd1ae): add device tree files
feat(rd1ae): introduce Arm RD-1 AE platform
build(bl2): enable check for bl2 base overflow assert
feat(arm): add support for loading CONFIG from BL2

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851df3c801-Oct-2024 Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

fix(versal2): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-I

fix(versal2): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: Iee222595962273913a570786ff1df5dc3ad328df
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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06f63f4b26-Sep-2024 Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

fix(versal-net): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Chang

fix(versal-net): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I20ef3be35f88649979d577ec8be4357813d4c1b7
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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ab9aab3826-Sep-2024 Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

fix(versal): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(versal): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: If3507f812ed4cfa518e6f5c5de977a76713fafd8
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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d3bb350c26-Sep-2024 Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

fix(xilinx): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(xilinx): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I1d369d977e0f2749024736d53fbb5c7d5555f6cb
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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1c43e36a18-Apr-2024 Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

fix(zynqmp): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id

fix(zynqmp): declare unused parameters as void

This corrects the MISRA violation C2012-2.7:
There should be no unused parameters in functions.
Declared unused function parameters as void.

Change-Id: I435dbcbe1c4aad7c69eb49599cd0dbca0677150d
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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e9529e4624-Sep-2024 Raghu Krishnamurthy <raghupathyk@nvidia.com>

refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e156457

refactor: digest sizes

The digest size in bytes for sha1/256/384/512 were defined in multiple
places. Refactor the macros into a common header file.

Change-Id: I84ef3561486ff70345ae8c871d5d6e1564574ec2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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764c66bb30-Sep-2024 Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

docs(build): update GCC to 13.3.Rel1 version

Updating toolchain to the latest production release version
13.3.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-down

docs(build): update GCC to 13.3.Rel1 version

Updating toolchain to the latest production release version
13.3.Rel1 publicly available on:
https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads

We build TF-A in CI using x86_64 Linux hosted cross toolchains:
---------------------------------------------------------------
* AArch32 bare-metal target (arm-none-eabi)
* AArch64 bare-metal target (aarch64-none-elf)

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: If5915fdc14a6c65ce58ac7fccfddd6fe85c0d7c9

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db7eb68821-May-2024 Ryan Everett <ryan.everett@arm.com>

fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits

fix(cpus): workaround for Cortex-X4 erratum 3076789

Cortex-X4 erratum 3076789 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2.

The workaround is to set chicken bits CPUACTLR3_EL1[14:13]=0b11
and CPUACTLR_EL1[52] = 1.
Expected performance degradation is < 0.5%, but isolated
benchmark components might see higher impact.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2432808/latest

Change-Id: Ib100bfab91efdb6330fdcdac127bcc5732d59196
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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8ee0fc3130-Sep-2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
paramet

fix(nxp-clk): function parameter should not be modified

The function 'update_stack_depth' modifies the value of the 'depth'
parameter passed by reference. Typically, the caller recevies this
parameter by value, and it is then passed to 'update_stack_depth' by
reference. This violates MISRA 17.8 rule. To address this issue, a new
local variable is introduced to store the value of 'depth'.

Change-Id: Ia37f4ede9e6558f778bdda17b7b195f1f50d0c30
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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8a4f840b17-Sep-2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87

feat(nxp-clk): enable the DDR clock

Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.

Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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