Merge "fix(docs): put INIT_UNUSED_NS_EL2 docs back" into integration

Merge "feat(stm32mp2): add FWU support" into integration

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32

Merge changes I7854e1ae,I214e4b2b,I000573e5 into integration

* changes:
feat(stm32mp2): add a runtime service for STGEN configuration
feat(stm32mp2): add common SMC runtime services
feat(stm32mp1): rework SVC services

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fix(trbe): add a tsb before context switching

Just like for SPE, we need to synchronize TRBE samples before we change
the context to ensure everything goes where it was intended to. If that
is not d

fix(trbe): add a tsb before context switching

Just like for SPE, we need to synchronize TRBE samples before we change
the context to ensure everything goes where it was intended to. If that
is not done, the in-flight entries might use any piece of now incorrect
context as there are no implicit ordering requirements.

Prior to root context, the buffer drain hooks would have done that. But
now that must happen much earlier. So add a tsb to prepare_el3_entry as
well.

Annoyingly, the barrier can be reordered relative to other instructions
by default (rule RCKVWP). So add an isb after the psb/tsb to assure that
they are ordered, at least as far as context is concerned.

Then, drop the buffer draining hooks. Everything they need to do is
already done by now. There's a notable difference in that there are no
dsb-s now. Since EL3 does not access the buffers or the feature
specific context, we don't need to wait for them to finish.

Finally, drop a stray isb in the context saving macro. It is now
absorbed into root context, but was missed.

Change-Id: I30797a40ac7f91d0bb71ad271a1597e85092ccd5
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(spe): add a psb before updating context and remove context saving

In the chapter about FEAT_SPE (D16.4 specifically) it is stated that
"Sampling is always disabled at EL3". That means that disab

fix(spe): add a psb before updating context and remove context saving

In the chapter about FEAT_SPE (D16.4 specifically) it is stated that
"Sampling is always disabled at EL3". That means that disabling sampling
(writing PMBLIMITR_EL1.E to 0) is redundant and can be removed. The only
reason we save/restore SPE context is because of that disable, so those
can be removed too.

There's the issue of draining the profiling buffer though. No new
samples will have been generated since entering EL3. However, old
samples might still be in-flight. Unless synchronised by a psb csync,
those might be affected by our extensive context mutation. Adding a psb
in prepare_el3_entry should cater for that. Note that prior to the
introduction of root context this was not a problem as context remained
unchanged and the hooks took care of the rest.

Then, the only time we care about the buffer actually making it to
memory is when we exit coherency. On HW_ASSISTED_COHERENCY systems we
don't have to do anything, it should be handled for us. Systems without
it need a dsb to wait for them to complete. There should be one already
in each cpu's powerdown hook which should work.

While on the topic of barriers, the esb barrier is no longer used.
Remove it.

Change-Id: I9736fc7d109702c63e7d403dc9e2a4272828afb2
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(drtm): adjust Event Log size in DLME

Updated the code to ensure the Event Log in the DLME meets
the minimum size requirement of 64KB, as specified in the
specification.

Change-Id: If0b179a97c0d

fix(drtm): adjust Event Log size in DLME

Updated the code to ensure the Event Log in the DLME meets
the minimum size requirement of 64KB, as specified in the
specification.

Change-Id: If0b179a97c0dca489edc0047da401bbb4ce09f39
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(tc): eliminate unneeded MbedTLS dependency" into integration

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unco

fix(tc): eliminate unneeded MbedTLS dependency

The rse_platform_api.h file includes certain MbedTLS headers,
introducing an unnecessary dependency when building the TC
platform with RSE support unconditionally.
However, these headers are not required, as the BL31
implementation only initializes RSE communication,
which does not rely on MbedTLS.

Change-Id: If45122aaf158be128f8978422fd870dbb0a0d090
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.cor

feat(mediatek): add vcp driver support

It is excepted that kernel vcp can request the vcp hw do
some security setting via SMC call services.

Signed-off-by: Xiangzhi Tang <xiangzhi.tang@mediatek.corp-partner.google.com>
Change-Id: Ib5c01c1d72b3483262dcd821878e6e53ba9c681c

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Merge changes from topic "hf_transfer_list" into integration

* changes:
fix(tlc): pass the flags from client interface
fix(tlc): relax entry addition from YAML files
feat(tlc): add --align arg

Merge changes from topic "hf_transfer_list" into integration

* changes:
fix(tlc): pass the flags from client interface
fix(tlc): relax entry addition from YAML files
feat(tlc): add --align argument
fix(tlc): add void entries to align data
fix(handoff): correct 8-bit modulo csum calculation
feat(tlc): formalise random generation of TEs

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fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build

fix(rk3399): fix unquoted .incbin for clang

While GCC doesn't complain about anything for .incbin, clang does:
"""
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0.bin""", "rk3399m0_bin", ".sram.incbin"
^
<instantiation>:6:10: error: expected string in '.incbin' directive
.incbin /build/rk3399/release/m0/rk3399m0pmu.bin
^
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21:1: note: while in macro instantiation
INCBIN """/build/rk3399/release/m0/rk3399m0pmu.bin""", "rk3399m0pmu_bin", ".pmusram.incbin"
^
"""

Adding quotes around \file in .incbin fixes the clang issue but GCC now
complains:
"""
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S: Assembler messages:
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:20: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: junk at end of line, first unrecognized character is `/'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:14: Error: unable to include `./'
plat/rockchip/rk3399/drivers/pmu/pmu_fw.S:21: Info: macro invoked from here
"""

Considering that the symbol is defined with escaped quotes, it is
probably safe to remove the double quotes around the INBCIN macro
parameter, so let's do that to make both compilers happy.

Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>
Change-Id: Id18b0341353ffc00e44e2d3c643ccdd05cc20c4f

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fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
do

fix(rk3399): mark INCBIN-generated sections as SHF_ALLOC

When assembling with Clang, sections generated via the `INCBIN` macro
are not assigned the `SHF_ALLOC` attribute, and the linker therefore
does not know to include them in the binary.

This change is simple: explicitly tell the assembler that the section
should have the `SHF_ALLOC` attribute.

For reference: https://man7.org/linux/man-pages/man5/elf.5.html

> SHF_ALLOC
> This section occupies memory during process execution. Some
> control sections do not reside in the memory image of an object
> file. This attribute is off for those sections.

Change-Id: I626162eae9030b5ffbd03af2be76f89a248af9ca
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de>

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Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
bui

Merge changes from topic "clang-rockchip" into integration

* changes:
build(rk3399): m0: Makefile: respect verbosity for linkerfile
build(rk3399): m0: fail linker and assembler on warnings
build(rk3399): m0: remove redundant M0_CROSS_COMPILE
feat(build): rk3399: m0: add support for new binutils versions
fix(rk3399): m0: Makefile: fix outside array bounds warning
refactor(rk3399): m0: Makefile: use same tools as in build_macros.mk
refactor(rk3399): m0: Makefile: specify ARCH to be rk3399-m0
fix(rk3588): pmu: fix assembly symbol redefinition
fix(rockchip): pmu: Do not mark already defined functions as weak
fix(rk3399): dram: Fix build with gcc 11
fix(rk3288): remove unused function
fix(px30): remove unused function

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fix(stm32mp1-fdts): re-enable RTC clock

On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.

Signed-off-by: Valentin

fix(stm32mp1-fdts): re-enable RTC clock

On STM32MP15 ST boards, RTC clock configuration by OPTEE is not ready
yet. Re-enable it temporary to get LSE as clock source of RTC.

Signed-off-by: Valentin Caron <valentin.caron@foss.st.com>
Change-Id: Ib6071229552e456faffb4fdfc8db9808140d54a7

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Merge "feat(tc): add devicetree node for AP/RSE MHU" into integration

Merge "fix(romlib): romlib build without MbedTLS" into integration

Merge "feat(tc): initialize MHU channels with RSE" into integration

Merge "fix(tc): map mem_protect flash region" into integration

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Th

feat(stm32mp2): add a runtime service for STGEN configuration

Other component such as OP-TEE may have the responsibility for
STGEN configuration but updating Arm CNTFRQ can only be done from
EL3. Therefore, implement a SiP SMC handler for this purpose and
a runtime service to catch SIP SMCs.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I7854e1ae6328f149798b43d52bb1ecdf71a5aa69

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feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Max

feat(stm32mp2): add common SMC runtime services

Implement the common SMC runtime services for stm32mp2 platforms.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I214e4b2bfba439572c079bbc9ffb62bc87793ce9

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feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-

feat(stm32mp1): rework SVC services

Having two generations of STM32MPX using the same SMCCC protocol,
rework the SVC services setup to put in common what can be put
in common and implement platform-specific handlers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I000573e50d55dc70163c2657c12cc84085416f6b

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Merge changes Ib1b810df,I5492bab5 into integration

* changes:
feat(tc): add dsu pmu node for TC4
feat(tc): enable DSU PMU el1 access for TC4

Merge "feat(qti): platform support for qcs615" into integration

feat(qti): platform support for qcs615

Change-Id: Ibbe78a196d77530fa9d94d7d12b2f08a4b66d62e
Signed-off-by: Amarinder Singh Sethi <quic_assethi@quicinc.com>

Merge "fix(cpus): workaround for Cortex-X4 erratum 2923985" into integration