Merge "feat(aarch64): add DBGPRCR_EL1 register accessors" into integration

feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id:

feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id: I72261fbf0395d900347b46af320093ed946aa73d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(drtm): adjust Event Log size in DLME" into integration

Merge "fix(cert-create): add default keysize to Brainpool ECDSA" into integration

Merge changes from topic "refactor-arm-key-files" into integration

* changes:
feat(mbedtls): optimize SHA256 for reduced memory footprint
refactor(arm): rename ARM_ROTPK_HEADER_LEN
docs(arm):

Merge changes from topic "refactor-arm-key-files" into integration

* changes:
feat(mbedtls): optimize SHA256 for reduced memory footprint
refactor(arm): rename ARM_ROTPK_HEADER_LEN
docs(arm): update docs to reflect rotpk key changes
feat(arm): use provided algs for (swd/p)rotpk
feat(arm): use the provided hash alg to hash rotpk

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fix(cert-create): add default keysize to Brainpool ECDSA

By default, the ECDSA Brainpool regular and ECDSA Brainpool twisted
algorithms support 256-bit sized keys. Not defining this leads to
an erro

fix(cert-create): add default keysize to Brainpool ECDSA

By default, the ECDSA Brainpool regular and ECDSA Brainpool twisted
algorithms support 256-bit sized keys. Not defining this leads to
an error indicating that '256' is not a valid key size for ECDSA
Brainpool. KEY_SIZES matrix must have a value in its table to avoid
problems when KEY_SIZE is defined.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I34886659315f59a9582dcee1d92d0e24d4a4138e

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feat(mbedtls): optimize SHA256 for reduced memory footprint

Set MBEDTLS_SHA256_SMALLER as the default mbedTLS configuration
to minimize memory usage, trading off some processing speed for
a smaller

feat(mbedtls): optimize SHA256 for reduced memory footprint

Set MBEDTLS_SHA256_SMALLER as the default mbedTLS configuration
to minimize memory usage, trading off some processing speed for
a smaller footprint.

Change-Id: Ibfa6e115a0ed94096b9acdd9e237f3fb5457071d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(arm): rename ARM_ROTPK_HEADER_LEN

This variable had a misleading name, as it is the length
of the header only when the ROTPK is a hash.
Also rename arm_rotpk_header to match the new pattern

refactor(arm): rename ARM_ROTPK_HEADER_LEN

This variable had a misleading name, as it is the length
of the header only when the ROTPK is a hash.
Also rename arm_rotpk_header to match the new pattern.

Change-Id: I36c29998eebf50c356a6ca959ec9223c8837b540
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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docs(arm): update docs to reflect rotpk key changes

The hashing algorithm for the rotpk is now HASH_ALG,
not always sha-256. The public development keys are
no longer in the repository and are now g

docs(arm): update docs to reflect rotpk key changes

The hashing algorithm for the rotpk is now HASH_ALG,
not always sha-256. The public development keys are
no longer in the repository and are now generated at
run-time, updates the documentation to reflect this.

Change-Id: Ic336f7aca858e9b6a1af6d6e6dc5f4aa428da179
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(arm): use provided algs for (swd/p)rotpk

No longer hard code SHA-256 hashed rsa dev keys,
now the keys can use pair of key alg: rsa, p256, p384
and hash alg: sha256, sha384, sha512.

All publi

feat(arm): use provided algs for (swd/p)rotpk

No longer hard code SHA-256 hashed rsa dev keys,
now the keys can use pair of key alg: rsa, p256, p384
and hash alg: sha256, sha384, sha512.

All public keys are now generated at build-time from the dev
keys.

Change-Id: I669438b7d1cd319962c4a135bb0e204e44d7447e
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(arm): use the provided hash alg to hash rotpk

No longer hard code SHA-256 hashed dev rotpks, instead
use the algorithm given by HASH_ALG. This means that
we no longer need the plat_arm_configs

feat(arm): use the provided hash alg to hash rotpk

No longer hard code SHA-256 hashed dev rotpks, instead
use the algorithm given by HASH_ALG. This means that
we no longer need the plat_arm_configs (once the protpk and
swd_rotpk are also updated to use HASH_ALG).

The rot public key is now generated at build time, as is
the header for the key.

Also support some default 3k and 4k RSA keys.

Change-Id: I33538124aeb4fa7d67918d878d17f2a84d3a6756
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(mediatek): refactor the data type of the return value

Change the data type regarding the return value of smc_handler_t

Change-Id: I208e7f131da8771ac2f41682ca0d97de468410ee
Signed-off-by: H

refactor(mediatek): refactor the data type of the return value

Change the data type regarding the return value of smc_handler_t

Change-Id: I208e7f131da8771ac2f41682ca0d97de468410ee
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>

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Merge changes Ic746571b,I1926cab9,Id70162e9,I3a9b014e,Ic99adba1, ... into integration

* changes:
feat(mt8196): enable APU on mt8196
feat(mt8196): add APU SMMU hardware semaphore operations
fea

Merge changes Ic746571b,I1926cab9,Id70162e9,I3a9b014e,Ic99adba1, ... into integration

* changes:
feat(mt8196): enable APU on mt8196
feat(mt8196): add APU SMMU hardware semaphore operations
feat(mt8196): add smpu protection for APU secure memory
feat(mt8196): add APU RCX DevAPC setting
feat(mt8196): add APU kernel control operations
feat(mt8196): add APU power on/off functions
feat(mt8196): add APUMMU setting
feat(mt8196): enable apusys mailbox mpu protection
feat(mt8196): enable apusys security control
feat(mt8196): add APUSYS AO DevAPC setting
feat(mt8196): add APU power-on init flow

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Merge "docs(maintainers): update marvell maintainer" into integration

Merge "fix(neoverse-rd): initialize timer before use in smmuv3_poll" into integration

fix(intel): handle cold reset via physical reset switch

On the Agilex5 platform when cold reset is issued via CLI application
in the OS, it is received in the BL31 via a SMC call and handled
accordi

fix(intel): handle cold reset via physical reset switch

On the Agilex5 platform when cold reset is issued via CLI application
in the OS, it is received in the BL31 via a SMC call and handled
accordingly like flush/invalidate the caches. However, when the cold
reset is issued via an external switch these handlings are missed.
This patch addresses those missed cache operations.

Also, this patch is to restoring SCR_EL3 NS bit to its previous value
in order to avoid unintended behavior especially if subsequent code
expects the SCR_EL3 register to be in its original configuration.

Change-Id: I9737f2db649e483ba61fffa6eeb0b56a9d15074a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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docs(maintainers): update marvell maintainer

Add Jaiprakash Singh as marvell maintainer

Change-Id: Ica924c0502b0a271b0368255841ef413391de959
Signed-off-by: Jaiprakash Singh <jaiprakashs@marvell.com>

fix(versal-net): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned

fix(versal-net): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "u" suffix to integer constant to represent it as
unsigned type.

Change-Id: I08b055134d6bd0380cca1e5b6ee527d6045a76c5
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned typ

fix(versal): add unsigned suffix to match data type

This corrects the MISRA violation C2012-7.2:
A “u” or “U” suffix shall be applied to all integer constants that
are represented in an unsigned type.
Appended "U" suffix to integer constant to represent it as
unsigned type.

Change-Id: I76f3c5903ed21ecba4d600e879d93026fc744f6c
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement bod

fix(versal2): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I546cf47edc6332ee193b4771c88ae30553687f19
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal-net): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement

fix(versal-net): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I8de33e774178720411313021a7b157045d3cefa0
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(zynqmp): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body

fix(zynqmp): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I8941f3c713586c36396e1f3731b99ffadc28c6e8
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_data_types" into integration

* changes:
fix(versal2): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(versal-

Merge changes from topic "xlnx_fix_plat_data_types" into integration

* changes:
fix(versal2): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal-net): typecast operands to match data type
fix(versal): typecast operands to match data type
fix(xilinx): typecast operands to match data type
fix(zynqmp): typecast operands to match data type
fix(versal2): typecast expressions to match data type
fix(versal-net): typecast expressions to match data type
fix(versal): typecast expressions to match data type
fix(xilinx): typecast expressions to match data type
fix(zynqmp): typecast expressions to match data type
fix(zynqmp): align essential type categories
fix(zynqmp): typecast expression to match data type
fix(xilinx): typecast expression to match data type

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fix(neoverse-rd): initialize timer before use in smmuv3_poll

Commit a6485b2 ("refactor(delay-timer): add timer callback
functions") introduced a requirement for timer-related APIs
to have a timer ob

fix(neoverse-rd): initialize timer before use in smmuv3_poll

Commit a6485b2 ("refactor(delay-timer): add timer callback
functions") introduced a requirement for timer-related APIs
to have a timer object initialized before use. This caused
assertion failures in SMMU routines on Neoverse platforms,
as they relied on timer APIs.

Resolve this issue by initializing the timer early during
platform boot to set up the timer_ops object properly.

Change-Id: I3d9ababdb7897185f23e9ccf982b9aab6c666b8c
Signed-off-by: Sammit Joshi <sammit.joshi@arm.com>

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fix(versal2): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(versal2): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I37ec9f8d716347df9acea5eb084f5a423a32a058
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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