fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., w

fix(stm32mp2): correct early/crash console init

The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.

To resolve this issue, 32-bit registers are now used for these
operations.

Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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chore(deps): add LTS Dependabot configuration

This is an experimental change which (hopefully) enables Dependabot on
the LTS branches, and ensures that PRs touching the package management
files in t

chore(deps): add LTS Dependabot configuration

This is an experimental change which (hopefully) enables Dependabot on
the LTS branches, and ensures that PRs touching the package management
files in the repository assign the proper developer(s) as reviewers.

Change-Id: Iefa2f46325514026969fabd08e550544dcb4a598
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com

fix(rdv3): fix comment for DRAM1 carveout size

Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB

Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95

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Merge "fix(spmd): fix build failure due to redefinition" into integration

Merge "feat(pmuv3): setup per world MDCR_EL3" into integration

Merge changes I95bb84b0,I2dfa62ac,I4017e44b into integration

* changes:
feat(stm32mp2-fdts): add STM32MP257F-DK board support
fix(stm32mp2-fdts): fix SDMMC slew rate
feat(stm32mp2-fdts): add L

Merge changes I95bb84b0,I2dfa62ac,I4017e44b into integration

* changes:
feat(stm32mp2-fdts): add STM32MP257F-DK board support
fix(stm32mp2-fdts): fix SDMMC slew rate
feat(stm32mp2-fdts): add LPDDR4 files

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feat(sptool): transfer list to replace SP Pkg

Generate the rules for calling 'tlc' tool, and generating
a partition package as a TL:
- The data is aligned to 4k.
- Using TE types 0x103 for FF-A mani

feat(sptool): transfer list to replace SP Pkg

Generate the rules for calling 'tlc' tool, and generating
a partition package as a TL:
- The data is aligned to 4k.
- Using TE types 0x103 for FF-A manifest, and 0x106 for
FF-A SP binary.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I1941e3e8f43d8dad33cdd0dea0571cf4a0d5e8f3

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feat(sptool): populate secure partition number in makefile

Calculate the secure partition number and saves it into the defined
macro NUM_SP.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-of

feat(sptool): populate secure partition number in makefile

Calculate the secure partition number and saves it into the defined
macro NUM_SP.

Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I4175a10d315482b65fd0f3eed4c6fd1e1e2b5e4d

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Merge changes Ided750de,Id3cc887c into integration

* changes:
docs(gxl): add build instructions for booting BL31 from U-Boot SPL
feat(gxl): add support for booting from U-Boot SPL/with standard

Merge changes Ided750de,Id3cc887c into integration

* changes:
docs(gxl): add build instructions for booting BL31 from U-Boot SPL
feat(gxl): add support for booting from U-Boot SPL/with standard params

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Merge "docs(maintainers): update LTS maintainers" into integration

docs(maintainers): update LTS maintainers

Updating LTS maintainers list as agreed with other LTS
maintainers.

Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <gov

docs(maintainers): update LTS maintainers

Updating LTS maintainers list as agreed with other LTS
maintainers.

Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(pmuv3): setup per world MDCR_EL3

MDCR_EL3 register will context switch across all worlds. Thus the pmuv3
init has to be part of context management initialization.

Change-Id: I10ef7a3071c0fc5c1

feat(pmuv3): setup per world MDCR_EL3

MDCR_EL3 register will context switch across all worlds. Thus the pmuv3
init has to be part of context management initialization.

Change-Id: I10ef7a3071c0fc5c11a93d3c9c2a95ec8c6493bf
Signed-off-by: Mateusz Sulimowicz <matsul@google.com>

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feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and

feat(versal2): update platform version to versal2

Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and version
information is also printed for chip identification.

Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge changes I10a3fc1d,I3aed6228 into integration

* changes:
fix(tc): set system-coherency to 0(ACE-LITE) for tc4-gpu
fix(tc): fix SMMU streamId for tc4 gpu

fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External L

fix(tc): enable Last-level cache (LLC) for tc4

EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,

External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.

On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.

Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>

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fix(rdn2): add LCA multichip data for RD-N2-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections

fix(rdn2): add LCA multichip data for RD-N2-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections to the correct downstream tx_cxs_a4s
port. The data programmed in the routing table are the A4S IDs
of each chip.

Change-Id: I46e558f3be7f0d51b768b7c5586f15e6bc517f3a
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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fix(rdv3): add LCA multichip data for RD-V3-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the ad

fix(rdv3): add LCA multichip data for RD-V3-Cfg2

This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the addresses programmed in the routing table is
the address of memory mapped HNI with chip offset.

Change-Id: Ic235983d63e8ab3492ae566b68841d0659724e45
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.

The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.

On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.

Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled

feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled dividers, the driver will attempt to adjust the division factor
to achieve the initially requested rate.

Change-Id: I7800c05b2f21bbdeda243db865942b647983687d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned ba

feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned based on the hardware state of the PLL module.

Change-Id: I3a270cbc92622ae82606382df1301597dc29782a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the paren

feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the parent object.

Change-Id: Id9e7fa49c3c1fb5b30b4c1b97fc8441bc967578a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM

feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM or PLL mux.

Change-Id: I24ae821013b0844e4d62793fde12b53b043a9776
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signe

feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Cha

feat(nxp-clk): add get_rate for s32cc_fixed_div

The get rate callback is needed for s32cc_fixed_div to allow the
frequency compilation for modules attached to a fixed divider like
LINFLEXD_CLK.

Change-Id: Ibc3e52f7f1127bba0dd793be0a26bdff15260824
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency

feat(nxp-clk): add get_rate for s32cc_dfs_div

Add the option to obtain the rate of an s32cc_dfs_div object. As in the
case of the PLL, the output divider of a DFS will return its targeted
frequency if the module is disabled and calculate the rate based on the
settings found in its registers if the module is turned on.

Change-Id: Id6db92dbdf03f8119875476ad8f7aa268ff6ea93
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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