Merge "feat(rmmd): verify FEAT_MEC present before calling plat hoook" into integration

docs: clarify multiple UUID support in ffa manifest

If a partition supports multiple UUID, the UUID property in the list
of partition properties in the FF-A manifest must be a list or array.
Update

docs: clarify multiple UUID support in ffa manifest

If a partition supports multiple UUID, the UUID property in the list
of partition properties in the FF-A manifest must be a list or array.
Update the document to clarify the same.

Change-Id: Id13fe8dbf57a00e5cd186158270b716a4a9aedf7
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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docs: clarify packing of UUID in ffa manifest

Update the ffa-manifest-bindings to clarify how the
Partition property 'UUID' must be packed.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Change

docs: clarify packing of UUID in ffa manifest

Update the ffa-manifest-bindings to clarify how the
Partition property 'UUID' must be packed.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Change-Id: Ic5ee67c9606dec30ed3a3234a5f40a976ecbb72c

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feat(rmmd): verify FEAT_MEC present before calling plat hoook

Some platforms do not support FEAT_MEC. Hence, they do not provide
an interface to update the update of the key corresponding to a
MECID

feat(rmmd): verify FEAT_MEC present before calling plat hoook

Some platforms do not support FEAT_MEC. Hence, they do not provide
an interface to update the update of the key corresponding to a
MECID.

This patch adds a condition in order to verify FEAT_MEC is present
before calling the corresponding platform hook, thus preventing it
from being called when the platform does not support the feature.

Change-Id: Ib1eb9e42f475e27ec31529569e888b93b207148c
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>

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Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in

Merge changes from topic "xlnx_fix_plat_invalid_entry" into integration

* changes:
fix(versal): handle invalid entry point in cpu hotplug scenario
fix(versal-net): handle invalid entry point in cpu hotplug scenario
fix(zynqmp): handle invalid entry point in cpu hotplug scenario

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fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by:

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by:

fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(spmd): check pwr mgmt status for SPMC framework response

The direct message response received by the SPMD upon a CPU_OFF power
management operation must be a framework message. If message indica

fix(spmd): check pwr mgmt status for SPMC framework response

The direct message response received by the SPMD upon a CPU_OFF power
management operation must be a framework message. If message indicates
SPMC denied the CPU_OFF operation, SPMD shall panic.

However, if SPMC does not support receiving power management
related framework messages from SPMD, it will return FFA_ERROR.
In such case, SPMD takes an implementation defined choice to ignore the
the FFA_ERROR and proceed with power management operation.

Change-Id: I18b9ee3fb8fd605bcd4aaa6802c969e9d36ccbe1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(guid-partition): initialise the mbr_entry variable

The compiler complains that it may be used unitialised. Give it some
confidence that won't be the case.

Change-Id: I14bddd48e4b205121415025175

fix(guid-partition): initialise the mbr_entry variable

The compiler complains that it may be used unitialised. Give it some
confidence that won't be the case.

Change-Id: I14bddd48e4b205121415025175f157b92a89aa26
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "refactor(mediatek): fix mcusys off issue for MTK GIC v3 driver" into integration

Merge "feat(rme): add SMMU and PCIe information to Boot manifest" into integration

feat(rme): add SMMU and PCIe information to Boot manifest

- Define information structures for SMMU, root complex,
root port and BDF mappings.
- Add entries for SMMU and PCIe root complexes to Boot

feat(rme): add SMMU and PCIe information to Boot manifest

- Define information structures for SMMU, root complex,
root port and BDF mappings.
- Add entries for SMMU and PCIe root complexes to Boot manifest.
- Update RMMD_MANIFEST_VERSION_MINOR from 4 to 5.

Change-Id: I0a76dc18edbaaff40116f376aeb56c750d57c7c1
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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fix(qemu): ignore TPM error

If firmware is configured with TPM support but it's missing
on HW, e.g. swtpm not started and/or configured with qemu,
then continue booting. Missing TPM is not a fatal e

fix(qemu): ignore TPM error

If firmware is configured with TPM support but it's missing
on HW, e.g. swtpm not started and/or configured with qemu,
then continue booting. Missing TPM is not a fatal error.
Enables testing boot without TPM device to see that
missing TPM is detected further up the SW stack and correct
fallback actions are taken.

Change-Id: Ibf35ae84383dc87ad65385ecb9e07fd81dce88f2
Signed-off-by: Mikko Rapeli <mikko.rapeli@linaro.org>

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style(clang-format): add Clang-Format configuration

Add a configuration for the Clang-Format C and C++ code style formatter.
This is based on the Clang-Format used by the Linux kernel with some
mino

style(clang-format): add Clang-Format configuration

Add a configuration for the Clang-Format C and C++ code style formatter.
This is based on the Clang-Format used by the Linux kernel with some
minor modifications:

- the for-each macros reflect what we have available in TF-A
- sorting of include files roughly follows our existing strategy

Change-Id: I8366c935a146175c14249e084a8328bbba05c7c8
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add li

Merge changes from topic "hm/handoff-aarch32" into integration

* changes:
refactor(arm): simplify early platform setup functions
feat(bl32): enable r3 usage for boot args
feat(handoff): add lib to sp-min sources
feat(handoff): add 32-bit variant of SRAM layout
feat(handoff): add 32-bit variant of ep info
fix(aarch32): avoid using r12 to store boot params
fix(arm): reinit secure and non-secure tls
refactor(handoff): downgrade error messages

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chore(versal2): realign address printing

Secure code address to be printed only when TF-A is
compiled with supported dispatcher service.

Change-Id: Ifb31f07981c00a9fddc7470aa991773266840400
Signed-

chore(versal2): realign address printing

Secure code address to be printed only when TF-A is
compiled with supported dispatcher service.

Change-Id: Ifb31f07981c00a9fddc7470aa991773266840400
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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fix(amd): update transfer list args for OP-TEE

Populate the boot arguments for handoff to OP-TEE, along with secure
endpoint information, from the transfer list only when
SPD is set to opteed.

Fix

fix(amd): update transfer list args for OP-TEE

Populate the boot arguments for handoff to OP-TEE, along with secure
endpoint information, from the transfer list only when
SPD is set to opteed.

Fix for MISRA Violation: MISRA-C:2012 R.14.4:
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.

Change-Id: I645205da3cb8ef9eea7d2c8d9a4200b485274e8a
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve in order in Cortex-X4
chore(cpus): rearrange the errata and cve in order in Neovers

Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve in order in Cortex-X4
chore(cpus): rearrange the errata and cve in order in Neoverse-V3

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Merge "chore(cpus): rearrange cve and errata order in Cortex-X3" into integration

Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): fix cve order in Neoverse-V2
chore(cpus): rearrange the errata and cve in order in Cortex-A710

Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus)

Merge changes from topic "ar/cvereorder" into integration

* changes:
chore(cpus): rearrange the errata and cve order in Neoverse-N2
chore(cpus): rearrange cve in order in Cortex-X1
chore(cpus): fix cve order in Neoverse-V1
chore(cpus): fix cve order in Cortex-X2
chore(cpus): fix cve order in Cortex-A78C
chore(cpus): fix cve order in Cortex-A78_AE
chore(cpus): fix cve order in Cortex-A78
chore(cpus): fix cve order in Cortex-A77

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Merge "refactor(cpus): don't panic if errata out of order" into integration

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-

chore(cpus): rearrange the errata and cve in order in Cortex-X4

Patch sorts the errata IDs in ascending order and the
CVE's in ascending order based on the year and index
for CPU Cortex-X4.

Change-Id: Ic304c2f68e7d0b96bbb30760696b7bceabe1ae2d
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe

chore(cpus): rearrange cve and errata order in Cortex-X3

Patch sorts the errata IDs in ascending order and the
CVE-2024-5660 in order based on the year and index
for Cortex-X3.

Change-Id: I2a4baebe0c3133528c089d999bdffa8c992f4989
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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