fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31

When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized,
leading to incorrect system counter frequency settings. This
impacted tim

fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31

When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized,
leading to incorrect system counter frequency settings. This
impacted timer-dependent components, such as SMMUv3, causing
initialization failures and unpredictable behavior.

To fix this, CNTFRQ_EL0 is now explicitly set using
plat_get_syscnt_freq2(), ensuring the correct system timer
frequency and proper initialization of dependent components.

Signed-off-by: Lokesh B V <Lokesh.BV@Arm.com>
Change-Id: I808b17d25c87c4dce1bc2c8171a800b69b5c2908

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fix(mt8196): remove EC_SUSPEND_PIN initial setting

Move EC_SUSPEND_PIN (GPIO_AP_SUSPEND_L) init to coreboot and remove
EC_SUSPEND_PIN init from TF-A.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.

fix(mt8196): remove EC_SUSPEND_PIN initial setting

Move EC_SUSPEND_PIN (GPIO_AP_SUSPEND_L) init to coreboot and remove
EC_SUSPEND_PIN init from TF-A.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I3d7a5a923dc9f692495d99255427a39ef5852bf8

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fix(mt8196): remove SPM support for ES chip

We no longer maintain the device equipped with ES chip. Remove SPM
support for ES ship.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I5

fix(mt8196): remove SPM support for ES chip

We no longer maintain the device equipped with ES chip. Remove SPM
support for ES ship.

Signed-off-by: Wenzhen Yu <wenzhen.yu@mediatek.com>
Change-Id: I5b2d035ec384a9861239f33dbe6df54c17f1285c

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feat(spm_mm): move mm_communication header define to general header

To support TPM start method with SIP, SIP handler dispatch request to
secure partition via MM_COMMUNICATE abi.
That means spm_mm s

feat(spm_mm): move mm_communication header define to general header

To support TPM start method with SIP, SIP handler dispatch request to
secure partition via MM_COMMUNICATE abi.
That means spm_mm sip handler should generate mm communication header.

Move mm_communication header's definition to spm_mm_svc header.

Change-Id: I40567c16e67b068ee83a39eff050d6578aecfb2c
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>

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fix(spmd): prevent SIMD context loss

When SPMD_SPM_AT_SEL2 is enabled, saving and restoring the SIMD context
is not needed because the SPMC handles it. The function
spmd_secure_interrupt_handler inc

fix(spmd): prevent SIMD context loss

When SPMD_SPM_AT_SEL2 is enabled, saving and restoring the SIMD context
is not needed because the SPMC handles it. The function
spmd_secure_interrupt_handler incorrectly restores the SWD SIMD context
before entering the SPMC without saving the NWD SIMD context, leading to
its loss. Furthermore, the SWD SIMD context is saved after returning
from the SPMC which is unnecessary.

This commit prevents the restoration of the SWD SIMD context before SPMC
entry and the saving of the SWD SIMD context after returning from the
SPMC when SPMD_SPM_AT_SEL2 is enabled. This ensures the preservation of
the NWD SIMD context.

Change-Id: I16a3e698e61da7019b3a670475e542d1690a5dd9
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>

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Merge changes from topic "gr/errata_mpidr" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 2963999
fix(cpus): workaround for Neoverse-V3 erratum 2970647
fix(cpus): wo

Merge changes from topic "gr/errata_mpidr" into integration

* changes:
fix(cpus): workaround for Cortex-X925 erratum 2963999
fix(cpus): workaround for Neoverse-V3 erratum 2970647
fix(cpus): workaround for Cortex-X4 erratum 2957258

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Merge changes from topic "mb/drtm" into integration

* changes:
fix(drtm): fix DLME data size check
fix(drtm): sort the address-map in ascending order
feat(libc): import qsort implementation

Merge "feat(mt8196): disable debug flag in APU driver" into integration

Merge changes I32bd0c71,I167e7398 into integration

* changes:
fix(arm): don't race on the build directory
fix(armada): don't race on the UART_IMAGE

fix(cpus): workaround for Cortex-X925 erratum 2963999

Cortex-X925 erratum 2963999 that applies to r0p0 and is fixed in
r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
whi

fix(cpus): workaround for Cortex-X925 erratum 2963999

Cortex-X925 erratum 2963999 that applies to r0p0 and is fixed in
r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/109180/latest/

Change-Id: I447fd359ea32e1d274e1245886e1de57d14f082c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Neoverse-V3 erratum 2970647

Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
whi

fix(cpus): workaround for Neoverse-V3 erratum 2970647

Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958/latest/

Change-Id: Iedf7d799451f0be58a5da1f93f7f5b6940f2bb35
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Cortex-X4 erratum 2957258

Cortex-X4 erratum 2957258 that applies to r0p0, r0p1 and is fixed in
r0p2.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
w

fix(cpus): workaround for Cortex-X4 erratum 2957258

Cortex-X4 erratum 2957258 that applies to r0p0, r0p1 and is fixed in
r0p2.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/109148/latest/

Change-Id: I2d8e7f4ce19ca2e1d87527c31e7778d81aff0279
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "docs(console): updated console docs" into integration

feat(rockchip): update uart baudrate for rk3399

Set the UART baudrate to 1500000 since that is what the ROM code and
other components use. This reverts the change of baudrate in the commit
0c05748bd

feat(rockchip): update uart baudrate for rk3399

Set the UART baudrate to 1500000 since that is what the ROM code and
other components use. This reverts the change of baudrate in the commit
0c05748bdebf ("rockchip: fixes for the required") and enables logging
from BL31 and OP-TEE during boot and after the kernel has booted.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5b5db25b069f3676ebb9dba2fa778601e05f1334

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docs(console): updated console docs

Add documentation for the console framework on how to go about
instantiating a new console and how to use these consoles in TF-A.
This includes BOOT, RUNTIME and

docs(console): updated console docs

Add documentation for the console framework on how to go about
instantiating a new console and how to use these consoles in TF-A.
This includes BOOT, RUNTIME and CRASH consoles.

Change-Id: I746d38f69f1b035d2e85d2589646e7fd67cb9cc3
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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Merge "chore(dependabot): further refine Dependabot configuration" into integration

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS t

Merge changes from topic "memory_bank" into integration

* changes:
fix(qemu): statically allocate bitlocks array
feat(qemu): update for renamed struct memory_bank
feat(fvp): increase GPT PPS to 1TB
feat(gpt): statically allocate bitlocks array
chore(gpt): define PPS in platform header files
feat(fvp): allocate L0 GPT at the top of SRAM
feat(fvp): change size of PCIe memory region 2
feat(rmm): add PCIe IO info to Boot manifest
feat(fvp): define single Root region

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refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <y

refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee1

refactor(arm): switch to rse_mbx_init

The rse_comms_init() function will be removed. The new function to use
is rse_mbx_init() for the MHU mailbox initialization.

Change-Id: I1932500ef71b6e895f0ee164ee9c2b58becf4409
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creatio

refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creation of a new file rse_comms_mhu.c. New APIs are created to
initialize the mailbox, get max message size and send and receive data.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I75dda77e1886beaa6ced6f92c311617125918cfa

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refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch

refactor(tc): add plat_rse_comms_init

The same way it is done for neoverse_rd, create a plat_rse_comms_init()
function to call rse_comms_init().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I12f3b8a38a5369decb4b97f8aceeb0dc81cbea28

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refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, M

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, MHUv1, MHUv2, MHUv3...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia72e590088ce62ba8c9009f341b6135926947bee

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Merge changes from topic "imx8mq_build_fix" into integration

* changes:
fix(imx8m): fix imx8mq build break
fix(imx8mq): fix imx8mq build break due to hab

Merge "fix(altera): add in support for agilex5 b0 jtag id" into integration

feat(mt8196): disable debug flag in APU driver

Disable the debug flag from the driver to reduce debugging messages.

Change-Id: I9444f64acbf684debab56d8226b14c6c01200ea4
Signed-off-by: Gavin Liu <ga

feat(mt8196): disable debug flag in APU driver

Disable the debug flag from the driver to reduce debugging messages.

Change-Id: I9444f64acbf684debab56d8226b14c6c01200ea4
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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