fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
a

fix(cpufeat): replace "bti" mnemonic with hint instructions

Older GNU binutils version require to specify at least "armv8.5-a" for
the ARM architecture revision to accept "bti" instructions in the
assembly code. Binutils v2.35 have relaxed this, since "bti" is in the
hint space, so is ignored on older cores and does NOT require a BTI
enabled core to execute.

To not exclude those older binutils versions (as shipped with Ubuntu
20.04), use the "hint" encoding for the "bti" instructions, which are
accepted regardless of the minimum architecture revision. Hide this
encoding in a macro, to make the "bti" usage more readable in the
source code.

Change-Id: I005586efd8974a3f2c7202896c881bb5fed07eea
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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fix(cpufeat): improve xpaci wrapper

Older toolchains seem to have trouble parsing a directive on the same
line as an instruction, so they choke on the separating semicolon:

/tmp/ccBwXW8I.s:93: Erro

fix(cpufeat): improve xpaci wrapper

Older toolchains seem to have trouble parsing a directive on the same
line as an instruction, so they choke on the separating semicolon:

/tmp/ccBwXW8I.s:93: Error: unknown architecture `armv8.3-a;'

Put the .arch directive on a line of its own, so that the assembler can
digest it.

Drop the comment on the way: xpaci is a FEAT_PAUTH instruction not
encoded in the hint space, so *every* toolchain needs to be allowed
ARMv8.3 level instructions, not just older ones.

Also we do not need to force x0 as the register, the compiler will pick
it automatically, so drop the register variable.

Change-Id: I0d4d74bcdac04aa86c565ad0455f62adf81febb5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "chore(tc): remove TC2 platform variant" into integration

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by

feat(spe): add support for FEAT_SPE_FDS

Allow access to PMSDSFR_EL1 register at NS-EL1 or NS-EL2 when
FEAT_SPE_FDS is implemented.

Change-Id: I538577cbfa5b5f242d5dbaeeace7b8e4ee6ffd03
Signed-off-by: James Clark <james.clark2@arm.com>

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feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot

The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable i

feat(mt8189): disable L3C shared SRAM if the bootloader is coreboot

The coreboot of MT8189 does not disable the L3C shared SRAM because the
ramstage still needs access to it. Therefore, we disable it at the
start of ATF.

Change-Id: If87223a1f41afd639859ff0ce80d4e64a9e02a2e
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>

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feat(arm): support boot info handoff and event log

Add support for processing boot arguments via Firmware
Handoff on Arm platforms. Update platform hooks to pass
boot info to BL31 and BL32 stages.

feat(arm): support boot info handoff and event log

Add support for processing boot arguments via Firmware
Handoff on Arm platforms. Update platform hooks to pass
boot info to BL31 and BL32 stages.

Enable parsing and dumping of an event log from the
transfer list when MEASURED_BOOT is enabled. This allows
measured boot testing in the secure world.

Also update BL32 sources to include event log support when
TSPD and measured boot are both enabled.

Change-Id: Ia310696d0e6cfe93d756bfb075e9fda08342c0a1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(arm): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure c

fix(arm): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface. Also, update the
prototype for arm_tsp_early_platform_setup to make use of these
arguments in common code.

Change-Id: I3831776be58d6ebf672890d0f30bbbd1780976f7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(xilinx): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensur

fix(xilinx): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface.

Change-Id: I428577c5e92911db3bc6f1ac81b127b44cb136e4
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(socionext): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
en

fix(socionext): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface.

Change-Id: I931f32985d1d46297e0d8c47f06e072f270c5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(msm8916): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensu

fix(msm8916): update tsp_early_platform_setup prototype

The prototype for tsp_early_platform_setup has been redefined. Update
the platform implementation to match the new function signature and
ensure compatibility with the updated TSP interface.

Change-Id: I2270a45f3f7a3d6f6dbc0ecd9f8a4fb56a6727f9
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(tsp): cascade boot arguments to platforms

Enable platforms to receive boot arguments passed to the TSP, allowing
them to make use of these parameters.

This is in preparation for supporting Fir

feat(tsp): cascade boot arguments to platforms

Enable platforms to receive boot arguments passed to the TSP, allowing
them to make use of these parameters.

This is in preparation for supporting Firmware Handoff within the TSP.

BREAKING CHANGE: The prototype for `tsp_early_platform_setup` has been
redefined. Platforms must update their implementations to match the new
function signature.

Change-Id: I4b5c6493bb62846aaa0d9e330d8aa06e6a0525a8
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maxi

feat(fvp): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maximum allocation for TB-FW configuration to accommodate
trusted boot entries.

Change-Id: I39d69d79434a366096dcf4fbdc5c434950170b78
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(arm): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maxi

feat(arm): port event log to firmware handoff

Support handing off the event log to both the secure and non-secure
worlds using the firmware handoff framework. This also needs us to
increase the maximum allocation for TB-FW configuration to accommodate
trusted boot entries.

Change-Id: I9f622b10c3cec2a9ab069f7848b00b1b635bd029
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): increase bl2 mmap len for handoff

With firmware handoff and OP-TEE the BL2 translation tables need to be
one entry longer than they currently are. Increase the current max
length by this

feat(fvp): increase bl2 mmap len for handoff

With firmware handoff and OP-TEE the BL2 translation tables need to be
one entry longer than they currently are. Increase the current max
length by this much to allow to build these two configurations together.

Change-Id: Ibb7a62e1ded1aded072bc248a08f008f1b286c45
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(measured-boot): add fw handoff event log utils

Add utilities for handling an event log from a transfer list. These
handle initialisation, and extension of an existing event log.

Change-Id: I42

feat(measured-boot): add fw handoff event log utils

Add utilities for handling an event log from a transfer list. These
handle initialisation, and extension of an existing event log.

Change-Id: I42d8b65a7fa82fa866d8ac258d9eeb58af730a96
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(mediatek): refactor Mediatek options.mk

Replace the individual `$(eval $(call add_defined_option, ... ))` lines
with a single `DEFINED_OPTIONS` variable.

Change-Id: I20303248e7531b8c2d6d4d

refactor(mediatek): refactor Mediatek options.mk

Replace the individual `$(eval $(call add_defined_option, ... ))` lines
with a single `DEFINED_OPTIONS` variable.

Change-Id: I20303248e7531b8c2d6d4d6492a1b768f7f3fc5c
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge "docs(rmmd): document the EL3-RMM IDE KM Interface" into integration

Merge "docs: updates for playbook" into integration

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch updates the documentation for the EL3-RMM IDE KM interface,
addressing errors found in the previous version and fixed formatting
issues a

docs(rmmd): document the EL3-RMM IDE KM Interface

This patch updates the documentation for the EL3-RMM IDE KM interface,
addressing errors found in the previous version and fixed formatting
issues and added missing details.

Change-Id: I84ff734d3de755fa793620e9b1446cf9b75763b0
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge changes from topic "ar/cve_wa_refactor" into integration

* changes:
refactor(cpus): optimize CVE checking
refactor(cpus): move errata check to common code
refactor(cpus): drop unused arg

Merge changes from topic "ar/cve_wa_refactor" into integration

* changes:
refactor(cpus): optimize CVE checking
refactor(cpus): move errata check to common code
refactor(cpus): drop unused argument forward_flag

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docs(versal-net): update documentation for SDEI

Update documentation to specify tf-a build option with SDEI support.

Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <

docs(versal-net): update documentation for SDEI

Update documentation to specify tf-a build option with SDEI support.

Change-Id: I6d3d8b1fc613e7207faccd9dd0ba517759bddf82
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported

feat(cpufeat): add support for FEAT_PAUTH_LR

This patch enables FEAT_PAUTH_LR at EL3 on systems that support it when
the new ENABLE_FEAT_PAUTH_LR flag is set.

Currently, PAUTH_LR is only supported by arm clang compiler and not GCC.

Change-Id: I7db1e34b661ed95cad75850b62878ac5d98466ea
Signed-off-by: John Powell <john.powell@arm.com>

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Merge "fix(sdei): return SDEI_EINVAL if signaling state is incorrect" into integration

docs: updates for playbook

Mention the dependencies than could be taken in TF-A.
Add a dedicated entry for the other repositories updates.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-I

docs: updates for playbook

Mention the dependencies than could be taken in TF-A.
Add a dedicated entry for the other repositories updates.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: If354105dcf94c0b305b8b6ac09822a4c42461e96

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refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* cal

refactor(cpus): optimize CVE checking

This patch replaces the use of EXTRA functions
with using erratum entries check
to verify CVE mitigation application for some of
the SMCCC_ARCH_WORKAROUND_* calls.

Previously, EXTRA functions were individually implemented for
each SMCCC_ARCH_WORKAROUND_*, an approach that becomes unmanageable
with the increasing number of workarounds.
By looking up erratum entries for CVE check, the process is streamlined,
reducing overhead associated with creating and
maintaining EXTRA functions for each new workaround.

New Errata entries are created for SMC workarounds and
that is used to target cpus that are uniquely impacted
by SMC workarounds.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I873534e367a35c99461d0a616ff7bf856a0000af

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