Merge pull request #344 from vwadekar/tegra-mselect-restore-v2

Tegra210: enable WRAP to INCR burst type conversions

Tegra210: enable WRAP to INCR burst type conversions

The Memory Select Switch Controller routes any CPU transactions to
the appropriate slave depending on the transaction address. During
system susp

Tegra210: enable WRAP to INCR burst type conversions

The Memory Select Switch Controller routes any CPU transactions to
the appropriate slave depending on the transaction address. During
system suspend, it loses all config settings and hence the CPU has
to restore them during resume.

This patch restores the controller's settings for enabling WRAP to
INCR burst type conversions on the master ports, for any incoming
requests from the AXI slave ports.

Tested by performing multiple system suspend cycles.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #342 from vwadekar/tlkd-delete-need-bl32-v1

tlkd: delete 'NEED_BL32' build variable

tlkd: delete 'NEED_BL32' build variable

Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_

tlkd: delete 'NEED_BL32' build variable

Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_BL32 flag does not influence the TLK load/boot
sequence at all. Moreover, it expects that TLK binary be present on
the host before we can compile BL31 support for Tegra.

This patch removes the flag from the makefile and thus decouples both
the build systems.

Tested by booting TLK without the NEED_BL32 flag.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #341 from vwadekar/tegra-denver-plat-support-v3

Tegra denver plat support v3

Tegra: modify 'BUILD_PLAT' to point to soc specific build dirs

This patch modifies the 'BUILD_PLAT' makefile variable to point to the soc
specific build directory in order to allow each Tegra soc to

Tegra: modify 'BUILD_PLAT' to point to soc specific build dirs

This patch modifies the 'BUILD_PLAT' makefile variable to point to the soc
specific build directory in order to allow each Tegra soc to have its own
build directory. This way we can keep the build outputs separate and can
keep multiple soc specific builds alive at the same time.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Support for Tegra's T132 platforms

This patch implements support for T132 (Denver CPU) based Tegra
platforms.

The following features have been added:

* SiP calls to switch T132 CPU's AARCH

Tegra: Support for Tegra's T132 platforms

This patch implements support for T132 (Denver CPU) based Tegra
platforms.

The following features have been added:

* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Add "Project Denver" CPU support

Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way supersca

Add "Project Denver" CPU support

Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent
micro-ops can be executed per clock), and includes a 128KB 4-way L1
instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
cache, which services both cores.

Denver implements an innovative process called Dynamic Code Optimization,
which optimizes frequently used software routines at runtime into dense,
highly tuned microcode-equivalent routines. These are stored in a
dedicated, 128MB main-memory-based optimization cache. After being read
into the instruction cache, the optimized micro-ops are executed,
re-fetched and executed from the instruction cache as long as needed and
capacity allows.

Effectively, this reduces the need to re-optimize the software routines.
Instead of using hardware to extract the instruction-level parallelism
(ILP) inherent in the code, Denver extracts the ILP once via software
techniques, and then executes those routines repeatedly, thus amortizing
the cost of ILP extraction over the many execution instances.

Denver also features new low latency power-state transitions, in addition
to extensive power-gating and dynamic voltage and clock scaling based on
workloads.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: implement per-SoC validate_power_state() handler

The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids

Tegra: implement per-SoC validate_power_state() handler

The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids are implementation
defined.

This patch moves the handler to the tegra/soc folder to allow each SoC to validate
the power_state for supported parameters.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: T210: include CPU files from SoC's platform.mk

This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only

Tegra: T210: include CPU files from SoC's platform.mk

This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only the required CPU files.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #337 from vwadekar/tegra-misc-fixes-v3

Tegra misc fixes v3

Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers.

Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: lock PMC registers holding CPU vector addresses

This patch locks access to the PMC registers which hold the CPU reset
vector addresses. The PMC registers are used by the warmboot code and

Tegra210: lock PMC registers holding CPU vector addresses

This patch locks access to the PMC registers which hold the CPU reset
vector addresses. The PMC registers are used by the warmboot code and
must be locked during boot/resume to avoid booting into custom firmware
installed by unknown parties e.g. hackers.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: PMC: lock SCRATCH22 register

The PMC Scratch22 register contains the CPU reset vector to
be used by the warmboot code to power up the CPU while resuming
from system suspend. This patch locks

Tegra: PMC: lock SCRATCH22 register

The PMC Scratch22 register contains the CPU reset vector to
be used by the warmboot code to power up the CPU while resuming
from system suspend. This patch locks this PMC register to avoid
any further writes.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: PMC: check if a CPU is already online

This patch checks if the target CPU is already online before
proceeding with it's power ON sequence.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra210: deassert CPU reset signals during power on

This patch de-asserts the CPU reset signals for each CPU as
part of it's power on sequence. This is needed to get rid of
the wait in BPMP firmwar

Tegra210: deassert CPU reset signals during power on

This patch de-asserts the CPU reset signals for each CPU as
part of it's power on sequence. This is needed to get rid of
the wait in BPMP firmware during SC7 exit.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: Fix the delay loop used during SC7 exit

This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g

Tegra: Fix the delay loop used during SC7 exit

This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0,
which would cause the loop to exit before it's expiry).

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: introduce delay timer support

This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.

Tegra: introduce delay timer support

This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge pull request #336 from danh-arm/sb/move-user-guide-to-linaro-release

Update user guide to use Linaro releases

Merge pull request #335 from jcastillo-arm/jc/sh_write

Fix bug in semihosting write function

Merge pull request #332 from jcastillo-arm/jc/tf-issues/214

Use uintptr_t as base address type in ARM driver APIs

Tegra: Exclude coherent memory region from memory map

This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.

Signed-off-by: V

Tegra: Exclude coherent memory region from memory map

This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Fix bug in semihosting write function

The return value from the SYS_WRITE semihosting operation is 0 if
the call is successful or the number of bytes not written, if there
is an error. The implement

Fix bug in semihosting write function

The return value from the SYS_WRITE semihosting operation is 0 if
the call is successful or the number of bytes not written, if there
is an error. The implementation of the write function in the
semihosting driver treats the return value as the number of bytes
written, which is wrong. This patch fixes it.

Change-Id: Id39dac3d17b5eac557408b8995abe90924c85b85

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TBB: rework cert_create tool to follow a data driven approach

This patch reworks the certificate generation tool to follow a data
driven approach. The user may specify at build time the certificates

TBB: rework cert_create tool to follow a data driven approach

This patch reworks the certificate generation tool to follow a data
driven approach. The user may specify at build time the certificates,
keys and extensions defined in the CoT, register them using the
appropiate macros and the tool will take care of creating the
certificates corresponding to the CoT specified.

Change-Id: I29950b39343c3e1b71718fce0e77dcf2a9a0be2f

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Update user guide to use Linaro releases

Linaro produce monthly software releases for the Juno and AEMv8-FVP
platforms. These provide an integrated set of software components
that have been tested t

Update user guide to use Linaro releases

Linaro produce monthly software releases for the Juno and AEMv8-FVP
platforms. These provide an integrated set of software components
that have been tested together on these platforms.

From now on, it is recommend that Trusted Firmware developers use the
Linaro releases (currently 15.06) as a baseline for the dependent
software components: normal world firmware, Linux kernel and device
tree, file system as well as any additional micro-controller firmware
required by the platform.

This patch updates the user guide to document this new process. It
changes the instructions to get the source code of the full software
stack (including Trusted Firmware) and updates the dependency build
instructions to make use of the build scripts that the Linaro releases
provide.

Change-Id: Ia8bd043f4b74f1e1b10ef0d12cc8a56ed3c92b6e

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