Merge "feat(fvp): give bootargs on all configs" into integration

Merge "feat(versal2): is OCM configured as coherent" into integration

fix(libc): explicitly check operators precedence

This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in p

fix(libc): explicitly check operators precedence

This corrects the MISRA violation C2012-12.1:
The precedence of operators within expressions should be
made explicit.
Enclosed the subexpression in parentheses to maintain
the precedence.

In spite of generic guidance for 3rd party libraries
(https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#misra-compliance)
libc contains some MISRA-C fixes done by commit d5ccb754af86
("libc: Fix some MISRA defects") in 2021.
Also from history it is not clear where libc is
coming from that's why there is no way to fix
violation in base library.

Change-Id: Ic985b418ecae6f61a0be10114deb6076caaa6e5f
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(fdts): add dual-ranked LPDDR4 config for STM32MP2

This adds support for a dual-ranked LPDDR4 variant with a total capacity
of 32Gbits, 32-bit bus widths, and 1200MHz frequency for the STM32MP2.

feat(fdts): add dual-ranked LPDDR4 config for STM32MP2

This adds support for a dual-ranked LPDDR4 variant with a total capacity
of 32Gbits, 32-bit bus widths, and 1200MHz frequency for the STM32MP2.

Change-Id: I7e506ca42196eb3eb4f98de007945865f95ee8e9
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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feat(st-pmic): add defines for NVM shadow registers

Change-Id: I28e194fbec7c7879bbbf46c602dc4587d74e31e9
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

refactor(st-pmic): use LOG_LEVEL for regulator debug output

The stpmic2_dump_regulators() function now uses LOG_LEVEL instead of
EVENT_LOG_LEVEL to align with general logging conventions.

Additiona

refactor(st-pmic): use LOG_LEVEL for regulator debug output

The stpmic2_dump_regulators() function now uses LOG_LEVEL instead of
EVENT_LOG_LEVEL to align with general logging conventions.

Additionally, the guard has been moved inside the function, removing
unnecessary preprocessor checks where the function is used and thereby
improving consistency.

Change-Id: I087de124e6795a599b4f91a7613c6dfa3f76bb7a
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>

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Merge changes from topic "versal2-qemu" into integration

* changes:
fix(versal2): align QEMU APU GT frequency with silicon
fix(zynqmp): fix syscnt frequency for QEMU

Merge "fix(cpus): remove errata setting PF_MODE to conservative" into integration

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2

Merge changes from topic "jc/tc_fw_handoff" into integration

* changes:
refactor(arm): simplify early platform setup function in BL31
refactor(arm): simplify early platform setup function in BL2
feat(arm): add support for Transfer List creation

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Merge changes I1dfb95aa,I9eb61c48 into integration

* changes:
feat(intel): support FCS commands with SiPSVC V3 framework
feat(intel): implementation of SiPSVC-V3 protocol framework

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off

fix(intel): update ssbl naming conventions

Update RSU SSBL name query in line with other bootloaders
and use secure string functions.

Change-Id: I8ae6b80eb74e91c6a82e59986cba137cf5ef6977
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>

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refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in

refactor(arm): simplify early platform setup function in BL31

Refactor `arm_bl31_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iff20300d2372e1a9825827ddccbd1b3bc6751e40

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refactor(arm): simplify early platform setup function in BL2

Refactor `arm_bl2_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
co

refactor(arm): simplify early platform setup function in BL2

Refactor `arm_bl2_early_platform_setup` to accept generic u_register_t
values, enabling support for firmware handoff boot arguments in
common code. This simplifies the interface for early platform setup.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie0dbe4d32bbef22bd185fdafe50091a2ea5f550f

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feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.

feat(arm): add support for Transfer List creation

This patch introduces Firmware Handoff support for Arm based
platforms listed under Firmware_Handoff specification.
[https://firmwarehandoff.github.io/firmware_handoff/main/transfer_list.html]

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ie3f30ffe38f809db907b663a8dbf1e48944ec690

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Merge "refactor: report features supported to secure world" into integration

docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the oth

docs(fvp): clarify what `FVP` means

An FVP, as a general Arm product, is a simulation of any kind of system.
This includes all such models from FVP_TC4, FVP_RD_V3, to FVP_Base and
others. On the other hand, an FVP as a TF-A platform means systems that
are compatible with FVP_Base. This, however, is an implicit assumption
and the term "FVP" causes ambiguity when used by TF-A developers and
interpreted by outsiders.

This patch makes this assumption explicit with a brief explanation of
the ambiguity and by specifically stating which FVPs are supported by
our fvp platform. For clarity, non-base models are removed from the list
as they have their own separate platform ports and dedicated
documentation.

Change-Id: Ie33671b09d951de0c6120061b2f4a084fd7e510a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(fvp): allow PSCI 0.2 in the device tree

Although the platform assumes it will use the device tree hosted with
it, there are device trees out there (eg in Linux) that will also work
just fine. So

fix(fvp): allow PSCI 0.2 in the device tree

Although the platform assumes it will use the device tree hosted with
it, there are device trees out there (eg in Linux) that will also work
just fine. Some of them, unfortunately, specify PSCI 0.2, but FCONF
performs a fatal check for 1.0. Add a fallback to 0.2 so that those
device trees can work.

Change-Id: I1543aa6d1dd12730299078500685928a13b16820
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(nxp-tools): fix2 create_pbl buildroot build" into integration

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A

fix(cpus): remove errata setting PF_MODE to conservative

The erratum titled “Disabling of data prefetcher with outstanding
prefetch TLB miss might cause a deadlock” should not be handled within
TF-A. The current workaround attempts to follow option 2 but
misapplies it. Specifically, it statically sets PF_MODE to
conservative, which is not the recommended approach. According to the
erratum documentation, PF_MODE should be configured in conservative
mode only when we disable data prefetcher however this is not done
in TF-A and thus the workaround is not needed in TF-A.

The static setting of PF_MODE in TF-A does not correctly address the
erratum and may introduce unnecessary performance degradation on
platforms that adopt it without fully understanding its implications.

To prevent incorrect or unintended use, the current implementation of
this erratum workaround should be removed from TF-A and not adopted by
platforms.

List of Impacted CPU's with Errata Numbers and reference to SDEN -

Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest
Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest
Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest
Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest
Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest
Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest
Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest
Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest

Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Chang

fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: I4ef0a040c14fdb2fbb3f2d9d4e6ca6ee8ac8e229

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fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa47

fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa4795fd5c69e

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refactor: report features supported to secure world

Report `FFA_MEM_PERM_GET` and `FFA_MEM_PERM_SET` supported to secure
world instances.

Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id:

refactor: report features supported to secure world

Report `FFA_MEM_PERM_GET` and `FFA_MEM_PERM_SET` supported to secure
world instances.

Signed-off-by: Karl Meakin <karl.meakin@arm.com>
Change-Id: I90e6b0ab601ae1142b419cacfa56109c183ab640

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fix(nxp-tools): fix2 create_pbl buildroot build

For some unknown reasons I did miss this '+' which does not make
sense when I submitted the former commit. We all did miss
it during codre reviews, so

fix(nxp-tools): fix2 create_pbl buildroot build

For some unknown reasons I did miss this '+' which does not make
sense when I submitted the former commit. We all did miss
it during codre reviews, sorry for the confusion. I do not understand
how it happened, late commits -> stupid issues.

Revert and fix: 634c7d81 fix create_pbl buildroot build
Wall -Werror -pedantic -std=c99 -O2 -DVERSION='"v2.12.0(release):master"' -D_GNU_SOURCE -D_XOPEN_SOURCE=700 -c -o create_pbl.o create_pbl.c
make[3]: Wall: No such file or directory

Change-Id: I1e17e4793061966ce5fa5e0c122914bfaed27952
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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Merge changes from topic "xlnx_fix_gen_datatype_cast" into integration

* changes:
fix(psci): add const qualifier
fix(el3-runtime): add const qualifier
fix(bl31): add const qualifier
fix(cons

Merge changes from topic "xlnx_fix_gen_datatype_cast" into integration

* changes:
fix(psci): add const qualifier
fix(el3-runtime): add const qualifier
fix(bl31): add const qualifier
fix(console): typecast expressions to match data type
fix(arm-drivers): typecast expressions to match data type
fix(arm-drivers): align essential type categories
fix(arm-drivers): typecast expression to match data type

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Merge "fix(guid-partition): initialise the mbr_entry variable" into integration