xlat lib: Reorganize architectural defs

Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows

xlat lib: Reorganize architectural defs

Move the header files that provide translation tables architectural
definitions from the library v2 source files to the library include
directory. This allows to share these definitions between both
versions (v1 and v2) of the library.

Create a new header file that includes the AArch32 or AArch64
definitions based on the AARCH32 build flag, so that the library user
doesn't have to worry about handling it on their side.

Also repurpose some of the definitions the header files provide to
concentrate on the things that differ between AArch32 and AArch64.
As a result they now contain the following information:
- the first table level that allows block descriptors;
- the architectural limits of the virtual address space;
- the initial lookup level to cover the entire address space.

Additionally, move the XLAT_TABLE_LEVEL_MIN macro from
xlat_tables_defs.h to the AArch32/AArch64 architectural definitions.

This new organisation eliminates duplicated information in the AArch32
and AArch64 versions. It also decouples these architectural files from
any platform-specific information. Previously, they were dependent on
the address space size, which is platform-specific.

Finally, for the v2 of the library, move the compatibility code for
ADDR_SPACE_SIZE into a C file as it is not needed outside of this
file. For v1, this code hasn't been changed and stays in a header
file because it's needed by several files.

Change-Id: If746c684acd80eebf918abd3ab6e8481d004ac68
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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FVP: Do not map DEVICE2 memory range when TBB is disabled

The DEVICE2 memory range is needed to access the Root of Trust Public
Key registers. This is not needed when Trusted Board Boot is disabled

FVP: Do not map DEVICE2 memory range when TBB is disabled

The DEVICE2 memory range is needed to access the Root of Trust Public
Key registers. This is not needed when Trusted Board Boot is disabled
so it's safer to not map it in this case. This also saves one level-2
page table in each of BL1 and BL2 images.

Also add some comments.

Change-Id: I67456b44f3fd5e145f6510a8499b7fdf720a7273
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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xlat lib v2: Print some debug statistics

This patch adds some debug prints to display some statistics about page
tables usage. They are printed only if the LOG_LEVEL is at least 50
(i.e. VERBOSE).

xlat lib v2: Print some debug statistics

This patch adds some debug prints to display some statistics about page
tables usage. They are printed only if the LOG_LEVEL is at least 50
(i.e. VERBOSE).

Sample output for BL1:

VERBOSE: Translation tables state:
VERBOSE: Max allowed PA: 0xffffffff
VERBOSE: Max allowed VA: 0xffffffff
VERBOSE: Max mapped PA: 0x7fffffff
VERBOSE: Max mapped VA: 0x7fffffff
VERBOSE: Initial lookup level: 1
VERBOSE: Entries @initial lookup level: 4
VERBOSE: Used 4 sub-tables out of 5 (spare: 1)

Change-Id: If38956902e9616cdcd6065ecd140fe21482597ea
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Fix CSS UART clock value

Fixes ARM-software/tf-issues#479

Change-Id: Iadbde2595ad6a0ac3988d17e614c698986959277
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Add doc for some Cortex A53 errata workarounds

Add documentation for errata 835769 and 843419 workarounds introduced in
commit a94cc374ab57b80d86974f8771565d65b38403ef

Fixes ARM-software/tf-issues#

Add doc for some Cortex A53 errata workarounds

Add documentation for errata 835769 and 843419 workarounds introduced in
commit a94cc374ab57b80d86974f8771565d65b38403ef

Fixes ARM-software/tf-issues#504

Change-Id: I7f3db53dfc5f3827b32663f483d3302bc9679b19
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

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Fix alphabetic ordering

Commit d832aee90, which added SPE support, got the alphabetical ordering
wrong for documentation and Makefile addition. This patch fixes that.

Change-Id: I061ecfba4db363902c

Fix alphabetic ordering

Commit d832aee90, which added SPE support, got the alphabetical ordering
wrong for documentation and Makefile addition. This patch fixes that.

Change-Id: I061ecfba4db363902c9d7d577d2ce6c612cb9e1d
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Merge pull request #1029 from islmit01/im/fix_includes

Fix order of includes

CSS: Prevent SCP_BL2/2U from overwriting BL1 RW data

On ARM CSS platforms, the SCP_BL2/2U image is loaded below
BL1 read-write data. This same memory is used to load BL31
later on. But sufficient ch

CSS: Prevent SCP_BL2/2U from overwriting BL1 RW data

On ARM CSS platforms, the SCP_BL2/2U image is loaded below
BL1 read-write data. This same memory is used to load BL31
later on. But sufficient checks were not done to ensure that the
SCP_BL2 would not overwrite BL1 rw data. This patch adds the
required CASSERT checks to prevent overwrite into BL1 or BL2
memory by load of SCP_BL2/2U. Also the size of BL31 is increased
and SCP_BL2/2U size is decreased to accomodate it within the
allocated region.

Change-Id: I23b28b5e1589e91150852a06452bd52b273216ee
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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CSS: Reorganize the SCP Image transfer functionality

The SCP_BL2 is transferred to SCP during BL2 image load and authenticate
sequence. The Boot-Over-MHU (BOM) protocol is used as transport for this

CSS: Reorganize the SCP Image transfer functionality

The SCP_BL2 is transferred to SCP during BL2 image load and authenticate
sequence. The Boot-Over-MHU (BOM) protocol is used as transport for this. After
the SCP boots using the transferred image, the AP CPU waits till the `READY`
message is received from SCP. This patch separates the API for transport of
image from the wait for `READY` message and also moves the related files to
the `css/drivers` folder. The previous API `scp_bootloader_transfer` is
renamed to `css_scp_boot_image_xfer` to reflect the css naming convention.
This reorganisation also allows easier switch to a different transport
(eg: Shared Data Structure based transfer) in future

Change-Id: I8a96f9c4616ffde6dbfdf7c18f6f6f8bfa40bbf0
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Resize the BL2 size limit for Juno

Recent patches to reduce the memory footprint of BL images have
resulted in saving several pages of memory. This patch reduces
the BL2 size limit by 20KB for Juno

Resize the BL2 size limit for Juno

Recent patches to reduce the memory footprint of BL images have
resulted in saving several pages of memory. This patch reduces
the BL2 size limit by 20KB for Juno when ARM_BOARD_OPTIMISE_MEM=1
so that more free space can be freed up for Trusted OS (BL32). Also
SCP_BL2/SCP_BL2U size is now restricted to 80K.

Change-Id: I1573d7a34e24d15e4abce8a14da40dbb5dc81e37
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Use standard UNIX file:line format in assert

This format is understood by almost all the UNIX tools (vi, emacs, acme, ...),
and it allows these tools to jump directly to the line where the assert
fa

Use standard UNIX file:line format in assert

This format is understood by almost all the UNIX tools (vi, emacs, acme, ...),
and it allows these tools to jump directly to the line where the assert
failed.

Change-Id: I648fa93c7cc65f911a17dcad5e1a775ac1ae5ed4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Clarify third party license info in readme

Clarify the license information for imported third party code in
the readme.rst file.

Change-Id: I96e26fda687a290a6dffb475aca20b169d85784d
Signed-off-by:

Clarify third party license info in readme

Clarify the license information for imported third party code in
the readme.rst file.

Change-Id: I96e26fda687a290a6dffb475aca20b169d85784d
Signed-off-by: Dan Handley <dan.handley@arm.com>

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Merge pull request #1005 from ldts/v1

Poplar: Initial commit for Poplar E-96Boards

Merge pull request #1028 from vchong/bl32_optee_support_v2

hikey: Add BL32 (OP-TEE) support v2

Poplar: Initial commit for Poplar E-96Boards

The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of

Poplar: Initial commit for Poplar E-96Boards

The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of running any commercial set-top solution based on
Linux or Android. Its high performance specification also supports a
premium user experience with up to H.265 HEVC decoding of 4K video at
60 frames per second.

SOC Hisilicon Hi3798CV200
CPU Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB Two USB 2.0 ports One USB 3.0 ports
CONSOLE USB-micro port for console support
ETHERNET 1 GBe Ethernet
PCIE One PCIe 2.0 interfaces
JTAG 8-Pin JTAG
EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI 802.11AC 2*2 with Bluetooth
CONNECTORS One connector for Smart Card One connector for TSI

The platform boot sequence is as follows:
l-loader --> arm_trusted_firmware --> u-boot

Repositories:
- https://github.com/Linaro/poplar-l-loader.git
- https://github.com/Linaro/poplar-u-boot.git

U-Boot is also upstream in the project's master branch.

Make sure you are using the correct branch on each one of these
repositories. The definition of "correct" might change over time (at
this moment in time this would be the "latest" branch).

Build Line:
make CROSS_COMPILE=aarch64-linux-gnu- all fip SPD=none DEBUG=1
PLAT=poplar BL33=/path/to/u-boot.bin

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Alex Elder <elder@linaro.org>
Tested-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Tested-by: Alex Elder <elder@linaro.org>

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Merge pull request #1027 from vchong/960_bl32_optee_support

hikey960 updates

Fix order of remaining platform #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupi

Fix order of remaining platform #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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Fix order of ARM platform #includes

This fix modifies the order of #includes in ARM standard platforms
to meet the ARM TF coding standard.

Change-Id: Ide19aad6233babda4eea2d17d49e523645fed1b2
Signe

Fix order of ARM platform #includes

This fix modifies the order of #includes in ARM standard platforms
to meet the ARM TF coding standard.

Change-Id: Ide19aad6233babda4eea2d17d49e523645fed1b2
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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hikey960: Add BL32 (OP-TEE) support

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Fix order of #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions in order to retain header groupings,
minimise changes to imported

Fix order of #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions in order to retain header groupings,
minimise changes to imported headers, and where there are headers within
the #if and #ifndef statements.

Change-Id: I65085a142ba6a83792b26efb47df1329153f1624
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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hikey: Add BL32 (OP-TEE) support

Signed-off-by: Victor Chong <victor.chong@linaro.org>

hikey: Remove unnecessary code

PLATFORM_LINKER_FORMAT
and
PLATFORM_LINKER_ARCH
defines are removed from
plat/hisilicon/hikey/include/platform_def.h
since there are already defined in
include/plat/co

hikey: Remove unnecessary code

PLATFORM_LINKER_FORMAT
and
PLATFORM_LINKER_ARCH
defines are removed from
plat/hisilicon/hikey/include/platform_def.h
since there are already defined in
include/plat/common/common_def.h
which is included by
plat/hisilicon/hikey/hikey_def.h
which is included by
plat/hisilicon/hikey/include/platform_def.h

The line
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
is removed from
plat/hisilicon/hikey/platform.mk
to clear the warning below:

Makefile:544: warning: overriding commands for target `check_SCP_BL2'
plat/hisilicon/hikey/platform.mk:19: warning: ignoring old commands for target `check_SCP_BL2'

$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
already exists in
Makefile
and applies to plat hikey so is redundant in
plat/hisilicon/hikey/platform.mk

Signed-off-by: Victor Chong <victor.chong@linaro.org>

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hikey: Fix errors in doc

Signed-off-by: Victor Chong <victor.chong@linaro.org>

hikey: Fix DDR_SIZE

Signed-off-by: Victor Chong <victor.chong@linaro.org>

hikey960: platform.mk: Remove FIP_ADD_IMG SCP_BL2

The line
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
is removed from
plat/hisilicon/hikey960/platform.mk
to clear the warning below:

Makefile:544:

hikey960: platform.mk: Remove FIP_ADD_IMG SCP_BL2

The line
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
is removed from
plat/hisilicon/hikey960/platform.mk
to clear the warning below:

Makefile:544: warning: overriding commands for target `check_SCP_BL2'
plat/hisilicon/hikey960/platform.mk:13: warning: ignoring old commands for
target `check_SCP_BL2'

$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
already exists in
Makefile
and applies to plat hikey960 so is redundant in
plat/hisilicon/hikey960/platform.mk

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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