feat(crypto): enable SIMD crypto extensions for S-EL1

Enable the SIMD in arch setup to enable SIMD crypto
extension for S-EL1 for BL2

Change-Id: I5573b5f214ca5d520ee45b380375df4c2344acf1
Signed-off

feat(crypto): enable SIMD crypto extensions for S-EL1

Enable the SIMD in arch setup to enable SIMD crypto
extension for S-EL1 for BL2

Change-Id: I5573b5f214ca5d520ee45b380375df4c2344acf1
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(psci): get the cpu_ops before exiting coherency" into integration

Merge changes I1eb8d262,I8e3e0ce6 into integration

* changes:
docs(arm): document BL2 mem params override
feat(arm): allow custom BL2 mem params

docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead o

docs(arm): document BL2 mem params override

Add documentation for the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag,
which allows platforms to supply their own
bl2_mem_params_desc.c implementation instead of using the common
Arm platform implementation.

Change-Id: I1eb8d262ba404f10a3cc2a0ff23bbc3f70041115
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri

feat(arm): allow custom BL2 mem params

Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.

Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge changes I49097cc1,Iad299bf9 into integration

* changes:
docs(rdaspen): measured boot support
feat(rdaspen): enable measured boot

fix(gpt): remove unused `gpt_disable` function

After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after b

fix(gpt): remove unused `gpt_disable` function

After GPT protections are enabled, there are no scenarios where they
need to be disabled, similarly to how TZC-400 protections are not
disabled after being setup.

Change-Id: I7eae3147130c7a6c3b7b3e9c10e8e7229f32505d
Signed-off-by: Ludovic Mermod <ludovic.mermod@arm.com>

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docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by

docs(rdaspen): measured boot support

Add optional measured boot support for RDaspen platform to enable
image and data measurement.

Change-Id: I49097cc1bbbda3c96a6ca22f1e7e76087b3ee856
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>

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feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f

feat(rdaspen): enable measured boot

Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.

Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f91
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "build(dev-deps): bump js-yaml in the dev-deps group across 1 directory" into integration

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- P

feat(rcar): add initial BL31 support for Renesas R-Car X5H

This patch introduces initial BL31 (EL3 firmware) support for the
Renesas R-Car Gen5 (X5H) platform.

Key features and changes include:
- Platform definitions and memory map for R-Car X5H
(Cortex-A720AE, 8 clusters x 4 cores)
- Platform-specific PSCI power management and topology
- SCMI-based power domain and system power management
- GICv4/Fainlight-AE interrupt controller initialization and support
- Trusted SRAM, shared memory, and crash log region setup
- SCIF console support
- Stack protector implementation for enhanced security
- Platform-specific linker script and build integration
- Various helper and initialization routines for MMU, GIC, and SCMI
- Platform-specific mailbox and boot flow handling
- Basic suspend implementation via SCP-FW
- AMU counters, SVE, PAUTH accessible to EL1

Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I04be48a55a618fe952b28283d2f85f48f7761c9a

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Merge "fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters" into integration

Merge "feat(build): enable link-time optimization by default" into integration

Merge "fix(gicv5): align IWB_WDOMAINR to the EAC spec" into integration

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimi

feat(build): enable link-time optimization by default

Enable LTO by default for all platforms and compilers. LTO performs
optimisation at link-time rather than at compilation time, and allows
optimisations to be made across compilation unit boundaries (i.e. C
files). This is especially useful in areas with lots of closely related
compilation units that operate on the same data structures (eg PSCI and
context management).

The only drawback is that LTO makes conditions ripe for the build to
heavily mangle all functions, making debugging a nightmare. So only
enable for release builds.

Note this will make object files unintepretable by objdump. Use lto-dump
instead.

BREAKING-CHANGE: LTO has been enabled by default, which may cause
unpredictable issues for platforms where the linker scripts have not
been designed with LTO in mind. Please report any issues to the
[mailing list](mailto:tf-a@lists.trustedfirmware.org).

Change-Id: Ia472aff1a23366d918abded7a1c5da695f2c4787
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
priva

fix(psci): get the cpu_ops before exiting coherency

It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.

So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.

Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I1

feat(neoverse-rd): set the correct Arm version for rdn2

The neoverse N2 and V2 cores in use on the platform are both v9
compliant. Declare the ARM_ARCH_{MAJOR, MINOR} to reflect this.

Change-Id: I15556fde3740056b1eb81138d19635b507064abf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(

Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(tspd): don't forward declare tsp_vectors_t
fix(cpufeat): drop feature_panic() as unused

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fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gicv5): align IWB_WDOMAINR to the EAC spec

The offset changed from 0x6000 to 0x8000.

Change-Id: I3a95e16c5379e2bb200a1ffaf40e3bae73288c5a
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

Merge "docs(changelog): changelog for v2.14 release" into integration

Merge "docs: update specification link in readme" into integration

docs: update specification link in readme

Change outdated links to the latest documentation for
PSCI, SMC Calling Convention, SCMI, and SDEI to ensure users have
access to the most current resources

docs: update specification link in readme

Change outdated links to the latest documentation for
PSCI, SMC Calling Convention, SCMI, and SDEI to ensure users have
access to the most current resources.

Change-Id: I2ee689d179a5d3ef96b55c45f52ace645ab52eb0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind

docs(changelog): changelog for v2.14 release

Generated this change-log using below command:
npm run release -- --skip.commit --skip.tag --release-as 2.14.0

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I3745f4506de123e3a4ff1e3ca6d5992f3b5c174a

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Merge "fix(changelog): fix platform order and add smcc to deprecated" into integration