Merge pull request #1503 from ARM-software/dh/dual-lic

Update license information in readme.rst

Merge pull request #1508 from sandrine-bailleux-arm/sb/fix-trusty-build

Fix handler prototype in Trusty generic dispatcher

psci: Use bool in internal interfaces

Change-Id: I77c9cd2d1d6d0122cc49917fa686014bee154589
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat: Use bool instead of int

Change-Id: I35d5b6a7c219f6f38983b30f157c1ed3808af17f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

mmc: add required delays when retrying commands

A new function mmc_reset_to_idle is also created.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge pull request #1507 from jeenu-arm/bool

Define bool type

Fix build for SEPARATE_CODE_AND_RODATA=0

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never define

Fix build for SEPARATE_CODE_AND_RODATA=0

TF won't build since no memory region is specified
for when SEPARATE_CODE_AND_RODATA=0 it still relies on
the ARM_MAP_BL_RO_DATA region which is never defined for
this case. Create memory region combining code and RO data for
when the build flag SEPARATE_CODE_AND_RODATA=0 to fix this

Change-Id: I6c129eb0833497710cce55e76b8908ce03e0a638
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Define bool type

This would enable us to write semantically sensible code.

Change-Id: Ie7c75f9c024f671a037448f5c0922174fff3f0ce
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Fix handler prototype in Trusty generic dispatcher

Fix the types of the arguments of trusty_generic_platform_smc()
to match the expected prototype of a runtime service handler
(see rt_svc_handle_t t

Fix handler prototype in Trusty generic dispatcher

Fix the types of the arguments of trusty_generic_platform_smc()
to match the expected prototype of a runtime service handler
(see rt_svc_handle_t type).

Change-Id: Ie839d116ca924b4b018ea2abbef72a1073da2a32
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #1500 from danielboulby-arm/db/RORedirection

Set console function pointers to const

Update license information in readme.rst

Added information on how disjunctively dual licensed code from
other projects is treated in the TF-A project.

Change-Id: Idca329abba4d36bd3c4fd722ac1556940b

Update license information in readme.rst

Added information on how disjunctively dual licensed code from
other projects is treated in the TF-A project.

Change-Id: Idca329abba4d36bd3c4fd722ac1556940b9135a2
Signed-off-by: Dan Handley <dan.handley@arm.com>

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Merge pull request #1498 from glneo/cache-early-fixes

Early cache enable and coherency fixes

Merge pull request #1493 from antonio-nino-diaz-arm/an/xlat-misra

Fix MISRA defects in xlat tables lib and SP805 driver

readme: Add information about the TF-A IRC channel

Fixes ARM-software/tf-issues#607

Change-Id: I5637f53e7f4857c85ee8b3af06ebcf86b9e4f1bc
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.

readme: Add information about the TF-A IRC channel

Fixes ARM-software/tf-issues#607

Change-Id: I5637f53e7f4857c85ee8b3af06ebcf86b9e4f1bc
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

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Set console function pointers to const

Set the function pointers in the console struct and the functions
they point to to const since they only need to be defined when
the console is being initialis

Set console function pointers to const

Set the function pointers in the console struct and the functions
they point to to const since they only need to be defined when
the console is being initialised and should not be changed after

Change-Id: I0574307111e3ab2f13d1a4a74c3fa75532dfa4be
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Fix MISRA defects in SP805 driver

Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4.

Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@a

Fix MISRA defects in SP805 driver

Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4.

Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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xlat: Fix MISRA defects

Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.

Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9

xlat: Fix MISRA defects

Fix defects of MISRA C-2012 rules 8.13, 10.1, 10.3, 10.4, 10.8, 11.6,
14.4, 15.7, 17.8, 20.10, 20.12, 21.1 and Directive 4.9.

Change-Id: I7ff61e71733908596dbafe2e99d99b4fce9765bd
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1497 from SNG-ARM/master

RAS changes for SGI575 platform

Merge pull request #1494 from hzhuang1/pcie_pin

Hikey960: configure pins for PCIe controller

Hikey960: configure pins for PCIe controller

GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.

Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Xiaowei

Hikey960: configure pins for PCIe controller

GPIO_089 connects to PCIE_PERST_N. It needs to be configured as
output low.

Signed-off-by: Kaihua Zhong <zhongkaihua@huawei.com>
Signed-off-by: Xiaowei Song <songxiaowei@hisilicon.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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ti: k3: common: Only enable caches early

We can enter and exit coherency without any software operations,
but HW_ASSISTED_COHERENCY has stronger implications that are
causing issues. Until these can

ti: k3: common: Only enable caches early

We can enter and exit coherency without any software operations,
but HW_ASSISTED_COHERENCY has stronger implications that are
causing issues. Until these can be resolved, only use the weaker
WARMBOOT_ENABLE_DCACHE_EARLY flag.

Signed-off-by: Andrew F. Davis <afd@ti.com>

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GIC: Do not flush cache when unneeded

When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.

Signed-off-b

GIC: Do not flush cache when unneeded

When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.

Signed-off-by: Andrew F. Davis <afd@ti.com>

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PSCI: Fix logic error to skip cache flushing

If either USE_COHERENT_MEM or HW_ASSISTED_COHERENCY being true
should cause us to not enter the ifdef block, then the logic
is not correct here. Posibly

PSCI: Fix logic error to skip cache flushing

If either USE_COHERENT_MEM or HW_ASSISTED_COHERENCY being true
should cause us to not enter the ifdef block, then the logic
is not correct here. Posibly bad use of De Morgan's law?
Fix this.

Signed-off-by: Andrew F. Davis <afd@ti.com>

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RAS: SGI: Add flags needed to build components for RAS feature

Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all fl

RAS: SGI: Add flags needed to build components for RAS feature

Add the various flags that are required to build the components needed
to enable the RAS feature on SGI575 platform. By default, all flags
are set to 0, disabling building of all corresponding components.

Change-Id: I7f8536fba895043ef6e397cc33ac9126cb572132
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>

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RAS: SGI575: Add platform specific RAS changes

Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used o

RAS: SGI575: Add platform specific RAS changes

Add platform specific changes needed to add support for the RAS
feature on SGI575 platform, including adding a mapping for the
CPER buffer being used on SGI575 platform.

Change-Id: I01a982e283609b5c48661307906346fa2738a43b
Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>

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