RAS: Fix assert condition

Change-Id: Ia02a2dbfd4e25547776e78bed40a91f3452553d7
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Merge pull request #1566 from EvanLloyd/non_secure_uart

ARM Platforms:Enable non-secure access to UART1

allwinner: implement system power down on H6 w/ AXP805

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original pla

allwinner: implement system power down on H6 w/ AXP805

The AXP805 PMIC used with H6 is capable of shutting down the system.

Add support for using it to shut down the system power.

The original placeholder power off code is moved to A64 code, as it's
still TODO to implement PMIC operations for A64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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allwinner: sun50i_h6: add initial AXP805 PMIC code

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.

Signed-off-by:

allwinner: sun50i_h6: add initial AXP805 PMIC code

The OTT reference design of Allwinner H6 SoC uses an X-Powers AXP805
PMIC.

Add initial code for it.

Currently it's only detected.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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Merge pull request #1565 from satheesbalya-arm/sb1_2332_fwu_sds_register

juno: Revert FWU update detect mechanism

allwinner: add I2C glue driver

Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller
core, with inverted clear quirk.

Add a glue driver for this.

Signed-off-by: Icenowy Zheng <ice

allwinner: add I2C glue driver

Allwinner 64-bit SoCs all use the Mentor Graphics MI2CV I2C controller
core, with inverted clear quirk.

Add a glue driver for this.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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drivers: mentor: mi2cv: add inverted interrupt clear flag quirk

The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marv

drivers: mentor: mi2cv: add inverted interrupt clear flag quirk

The I2C controller on Allwinner SoCs after A31 has a inverted interrupt
clear flag, which needs to be written 1 (rather than 0 on Marvell SoCs
and old Allwinner SoCs) to clear.

Add such a quirk to mi2cv driver common code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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allwinner: call PMIC setup code

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prev

allwinner: call PMIC setup code

As the ATF may need to do some power initialization on Allwinner
platform with AXP PMICs, call the PMIC setup code in BL31.

Stub of PMIC setup code is added, to prevent undefined reference.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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Merge pull request #1563 from jts-arm/mbed

Improvements to Mbed TLS shared heap code

Merge pull request #1564 from jeenu-arm/sdei-suspend

SDEI: Mask events after CPU wakeup

juno: Revert FWU update detect mechanism

The patch 7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this

juno: Revert FWU update detect mechanism

The patch 7b56928 unified the FWU mechanism on FVP and Juno
platforms due to issues with MCC firmware not preserving the
NVFLAGS. With MCCv150 firmware, this issue is resolved. Also
writing to the NOR flash while executing from the same flash
in Bypass mode had some stability issues. Hence, since the
MCC firmware issue is resolved, this patch reverts to the
NVFLAGS mechanism to detect FWU. Also, with the introduction
of SDS (Shared Data Structure) by the SCP, the reset syndrome
needs to queried from the appropriate SDS field.

Change-Id: If9c08f1afaaa4fcf197f3186887068103855f554
Signed-off-by: Sathees Balya <sathees.balya@arm.com>
Signed-off-by: Soby Mathew <Soby.Mathew@arm.com>

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Readjust BL2 size after sharing Mbed TLS heap

After introducing the Mbed TLS shared heap optimisation, reducing BL2
size by 3 pages didn't leave enough space for growth. We give 1 page
back to maxim

Readjust BL2 size after sharing Mbed TLS heap

After introducing the Mbed TLS shared heap optimisation, reducing BL2
size by 3 pages didn't leave enough space for growth. We give 1 page
back to maximum BL2 size.

Change-Id: I4f05432f00b923693160f69a4e4ec310a37a2b16
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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ARM Platforms:Enable non-secure access to UART1

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial

ARM Platforms:Enable non-secure access to UART1

Adds an undocumented build option that enables non-secure access to
the PL011 UART1.
This allows a custom build where the UART can be used as a serial debug
port for WinDbg (or other debugger) connection.

This option is not documented in the user guide, as it is provided as a
convenience for Windows debugging, and not intended for general use.
In particular, enabling non-secure access to the UART might allow
a denial of service attack!

Change-Id: I4cd7d59c2cac897cc654ab5e1188ff031114ed3c
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

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Add cache flush after BL1 writes heap info to DTB

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memor

Add cache flush after BL1 writes heap info to DTB

A cache flush is added in BL1, in Mbed TLS shared heap code. Thus, we
ensure that the heap info written to the DTB always gets written back to
memory. Hence, sharing this info with other images is guaranteed.

Change-Id: I0faada31fe7a83854cd5e2cf277ba519e3f050d5
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Additional runtime check for DTB presence in BL2

In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to

Additional runtime check for DTB presence in BL2

In Mbed TLS shared heap code, an additional sanity check is introduced
in BL2. Currently, when BL2 shares heap with BL1, it expects the heap
info to be found in the DTB. If for any reason the DTB is missing, BL2
cannot have the heap address and, hence, Mbed TLS cannot proceed. So,
BL2 cannot continue executing and it will eventually crash. With this
change we ensure that if the DTB is missing BL2 will panic() instead of
having an unpredictable crash.

Change-Id: I3045ae43e54b7fe53f23e7c2d4d00e3477b6a446
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Slight improvements in Mbed TLS shared heap helpers

This patch, firstly, makes the error messages consistent to how printed
strings are usually formatted. Secondly, it removes an unnecessary #if
dir

Slight improvements in Mbed TLS shared heap helpers

This patch, firstly, makes the error messages consistent to how printed
strings are usually formatted. Secondly, it removes an unnecessary #if
directive.

Change-Id: Idbb8ef0070562634766b683ac65f8160c9d109e6
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge pull request #1562 from antonio-nino-diaz-arm/an/bl31-warn

Convert BL31 error message into warning

SDEI: Mask events after CPU wakeup

The specification requires that, after wakeup from a CPU suspend, the
dispatcher must mask all events on the CPU. This patch adds the feature
to the SDEI dispatche

SDEI: Mask events after CPU wakeup

The specification requires that, after wakeup from a CPU suspend, the
dispatcher must mask all events on the CPU. This patch adds the feature
to the SDEI dispatcher by subscribing to the PSCI suspend to power down
event, and masking all events on the PE.

Change-Id: I9fe1d1bc2a58379ba7bba953a8d8b275fc18902c
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Convert BL31 error message into warning

If BL32 isn't present or it fails to initialize the current code prints
an error message in both debug and release builds. This is too verbose
for release bui

Convert BL31 error message into warning

If BL32 isn't present or it fails to initialize the current code prints
an error message in both debug and release builds. This is too verbose
for release builds, so it has been converted into a warning.

Also, it was missing a newline at the end of the message.

Change-Id: I91e18d5d5864dbb19d47ecd54f174d2d8c06296c
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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drivers: mentor: extract MI2CV driver from Marvell driver

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of custom

drivers: mentor: extract MI2CV driver from Marvell driver

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.

Extract the common code to a MI2CV driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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marvell: drivers: use anonymous union in I2C driver

The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor

marvell: drivers: use anonymous union in I2C driver

The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor customization, and the original IP core by Mentor Graphics uses
two different addresses for the two registers.

Use anonymous union in the driver, in order to ease code sharing for
other SoC vendors that use this IP core (Allwinner SoCs that are newly
introduced to mainline ATF use this core).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

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Merge pull request #1561 from jeenu-arm/bakery-barrier

Add missing barriers to Bakery Locks

Merge pull request #1558 from jenswi-linaro/qemu-update

Qemu updates

Add missing barriers to Bakery Locks

With the current implementation, it's possible for a contender to
observe accesses in the Critical Section before acquiring or releasing
the lock. Insert fencing

Add missing barriers to Bakery Locks

With the current implementation, it's possible for a contender to
observe accesses in the Critical Section before acquiring or releasing
the lock. Insert fencing in the locking and release codes to prevent any
reorder.

Fixes ARM-software/tf-issues#609

Change-Id: I773b82aa41dd544a2d3dbacb9a4b42c9eb767bbb
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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ARMv7: Alias dmbld() to dmb()

'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.

Change-Id: I502f360cb6412897ca9580b

ARMv7: Alias dmbld() to dmb()

'dmb ld' is not a recognized instruction for ARMv7. Since generic code
may use 'dmb ld', alias it to 'dmb' when building for ARMv7.

Change-Id: I502f360cb6412897ca9580b725d9f79469a7612e
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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