Tegra: pmc: helper function to find last ON CPU

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: Var

Tegra: pmc: helper function to find last ON CPU

This patch adds a helper function to find the last standing CPU
in a cluster.

Change-Id: Id018f1958f458c772c7b0c52af8ddf7532b1cec5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the pla

Tegra: platform dependent address space sizes

This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.

Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: Steven Kao <skao@nvidia.com>

show more ...

Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been mo

Tegra: organize memory/mmio apertures to decrease memmap latency

This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.

Change-Id: I6fdaee392f7ac5d99daa182380ca9116a001f5d6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow

Tegra210: Enable WDT_CPU interrupt for FIQ Debugger

This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.

Change-Id: I9437b516da2c5d763eca72694ed7f3c7389b3d9e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock()

Tegra: flowctrl: helper functions to assist with cluster power states

This patch adds helper functions to help platforms with cluster state entry
and exit decisions.

* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?

Change-Id: I6490d34bf380dc03ae203eb3028f61984f06931c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every clust

Tegra: bpmp: remove bpmp init failed error print

This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every cluster idle and powerdown request,
cluttering the logs.

Change-Id: I9e30007a913080406052fc32d5360ff70a019d75
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

tlkd: support new TLK SMCs

This patch adds support to handle following TLK SMCs:
{TLK_SS_REGISTER_HANDLER, TLK_REGISTER_NS_DRAM_RANGES, TLK_SET_ROOT_OF_TRUST}

These SMCs need to be supported in ATF

tlkd: support new TLK SMCs

This patch adds support to handle following TLK SMCs:
{TLK_SS_REGISTER_HANDLER, TLK_REGISTER_NS_DRAM_RANGES, TLK_SET_ROOT_OF_TRUST}

These SMCs need to be supported in ATF in order to forward them to
TLK. Otherwise, these functionalities won't work.

Brief:
TLK_SS_REGISTER_HANDLER: This SMC is issued by TLK Linux Driver to
set up secure storage buffers.

TLK_REGISTER_NS_DRAM_RANGES: Cboot performs this SMC during boot to
pass NS memory ranges to TLK.

TLK_SET_ROOT_OF_TRUST: Cboot performs this SMC during boot to pass
Verified Boot parameters to TLK.

Change-Id: I18af35f6dd6f510dfc22c1d1d1d07f643c7b82bc
Reviewed-on: https://git-master.nvidia.com/r/1643851
Signed-off-by: Mihir Joshi <mihirj@nvidia.com>

show more ...

Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT

Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs

This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.

Change-Id: I0752ef54a986c58305e1bc8ad9be71d4a8bbd394
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the fl

Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing

On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.

This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.

Change-Id: Idd07c88c8d730b5f0e93e3a6e4fdc59bdcb2161b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There

Tegra: SiP: set GPU in reset after vpr resize

Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.

This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.

Change-Id: I38a1000e3803f80909efcb02e27da4bd46909931
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

show more ...

Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

C

Tegra: handle FIQ interrupts when NS handler is not registered

This patch updates the secure interrupt handler to mark the interrupt
as complete in case the NS world has not registered a handler.

Change-Id: Iebe952305f7db46375303699b6150611439475df
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: bpmp_ipc: support to enable/disable module clocks

This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports

Tegra: bpmp_ipc: support to enable/disable module clocks

This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.

Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90
Signed-off-by: steven kao <skao@nvidia.com>

show more ...

Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the

Tegra: fix offset used to dump GICD registers from crash handler

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra: default platform handler for the CPU_STANDBY state

This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with thei

Tegra: default platform handler for the CPU_STANDBY state

This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.

Change-Id: I91e513842f194b1e2b1defa2d833bb4d9df5f06b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs t

Tegra186: smmu: add support for backup multiple smmu regs

Modifying smmu macros to pass base address of smmu so that it can be
used with multiple smmus.

Added macro for combining smmu backup regs that can be used for multiple
smmus.

Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

show more ...

User Guide: Move ARM_PLAT_MT doc to Arm build flags

ARM_PLAT_MT build flag is specific to Arm platforms so should not
be classified as a common build option.

Change-Id: I79e411958846759a5b60d770e53

User Guide: Move ARM_PLAT_MT doc to Arm build flags

ARM_PLAT_MT build flag is specific to Arm platforms so should not
be classified as a common build option.

Change-Id: I79e411958846759a5b60d770e53f44bbec5febe6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

Remove dead code related to LOAD_IMAGE_V2=0

Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended
to remove all code related to LOAD_IMAGE_V2=0 but missed a few things.

Change-Id: I

Remove dead code related to LOAD_IMAGE_V2=0

Commit ed51b51f7a9163a ("Remove build option LOAD_IMAGE_V2") intended
to remove all code related to LOAD_IMAGE_V2=0 but missed a few things.

Change-Id: I16aaf52779dd4af1e134e682731328c5f1e5d622
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

hikey960: EDMAC: leave channel 0 as secure

Channel 0 is used to communicate with LPM3, a coprocessor
for power management. Leave it as secure.

Signed-off-by: Ryan Grachek <ryan@edited.us>

Merge pull request #1798 from pbeesley-arm/pb/fix-code-style

doc: Fix broken code blocks in coding guidelines

doc: Fix broken code blocks in coding guidelines

Sections 2.2, 2.3 and 2.4 contained example code blocks that were not
being formatted properly due to missing newlines.

Change-Id: I0dbce90c931cf69e

doc: Fix broken code blocks in coding guidelines

Sections 2.2, 2.3 and 2.4 contained example code blocks that were not
being formatted properly due to missing newlines.

Change-Id: I0dbce90c931cf69e4f47d2ccbcc8bc0e20f8fd66
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

show more ...

Merge pull request #1797 from antonio-nino-diaz-arm/an/remove-smccc-v2

Remove support for the SMC Calling Convention 2.0

Merge pull request #1745 from svenauhagen/bugfix/a8k

Armada8k GPIO Register macro fix

Merge pull request #1793 from marex/arm/master/fixes-v2.0.0

Arm/master/fixes v2.0.0

Merge pull request #1792 from satheesbalya-arm/sb1/sb1_2159_v84_xlat

lib/xlat_tables: Add support for ARMv8.4-TTST

Merge pull request #1795 from pbeesley-arm/pb/code-style

Move coding guidelines into docs directory