Merge pull request #1884 from AlexeiFedorov/af/set_march_to_arch_minor

Allow setting compiler's target architecture

Merge pull request #1882 from ambroise-arm/av/a15-errata

Apply workarounds for errata of Cortex-A15

Merge pull request #1881 from sandrine-bailleux-arm/sb/doc-fixes

Minor doc fixes

Merge pull request #1880 from lmayencourt/lm/pie

PIE: fix linking with pie and binutils > 2.27

Merge pull request #1879 from pbeesley-arm/pb/todo-removal

Pb/todo removal

Merge pull request #1878 from jts-arm/sctlr

Apply stricter speculative load restriction

Merge pull request #1874 from hadi-asyrafi/qspi_boot

intel: QSPI boot enablement

Merge pull request #1873 from hadi-asyrafi/driver_qspi

intel: Add driver for QSPI

Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursion

Remove recursion from xlat_tables_v2 library

Merge pull request #1858 from thloh85-intel/dwmmc_fixes

drivers: synopsys: Fix synopsys MMC driver

Merge pull request #1856 from masahisak/synquacer-scmi-support

plat/synquacer: enable SCMI support

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1]

Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Cortex-A15: Implement workaround for errata 816470

Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

Merge pull request #1877 from bryanodonoghue/integration+bl2-el3-eret-fix-v2

bl2-el3: Fix exit to bl32 by ensuring full write to SPSR

Merge pull request #1861 from Yann-lms/checkpatch

Update checkpatch options

Merge pull request #1875 from Yann-lms/bsec

fdts: stm32mp1: add bsec node

bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed

A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate

bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed

A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.

The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.

msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.

This change ensures we capture the x field, which we are interested in and
not the f field which we are not.

Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1')

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.

This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.

Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image")

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>

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intel: QSPI boot enablement
Manages QSPI initialization, configuration and IO handling as boot device

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>

plat: imx8m: Add the basic support for imx8mm

The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-a

plat: imx8m: Add the basic support for imx8mm

The i.MX8M Mini is new SOC of the i.MX8M family. it is
focused on delivering the latest and greatest video and
audio experience combining state-of-the-art media-specific
features with high-performance processing while optimized
for lowest power consumption. The i.MX 8M Mini Media Applications
Processor is 14nm FinFET product of the growing i.MX8M family
targeting the consumer & industrial market. It is built in 14LPP
to achieve both high performance and low power consumption
and relies on a powerful fully coherent core complex based on
a quad Cortex-A53 cluster with video and graphics accelerators

this patch add the basic support for i.MX8MM.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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intel: Add driver for QSPI
To support the enablement of QSPI booting

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>

plat/arm: mhu: make mhu driver generic

MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic

plat/arm: mhu: make mhu driver generic

MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

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plat/synquacer: enable SCMI support

Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific

plat/synquacer: enable SCMI support

Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>

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Allow setting compiler's target architecture

Change-Id: I56ea088f415bdb9077c385bd3450ff4b2cfa2eac
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Makefile: fix linking with pie and binutils > 2.27

Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:

aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough

Makefile: fix linking with pie and binutils > 2.27

Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:

aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough room
for program headers, try linking with -N
aarch64-linux-gnu-ld: final link failed: Bad value

This issue was also encountered by u-boot[2] and linux powerpc kernel
[3]. The fix is to provide --no-dynamic-linker for the linker. This
tells the linker that PIE does not need loaded program program headers.

Fix https://github.com/ARM-software/tf-issues/issues/675

[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] http://git.denx.de/?p=u-boot.git;a=commit;h=e391b1e64b0bd65709a28a4764afe4f32d408243
[3] https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0a

Change-Id: Ic3c33c795a9b7bdeab0e87c4345153ce2703a524
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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