| 551631aa | 11-Apr-2019 |
Paul Beesley <paul.beesley@arm.com> |
plat/sgm: Remove redundant platform_oid.h
This file is used when building the cert_create tool without using the 'standard' set of Arm OID values as defined in the TBBR specification (see tbbr_oid.h
plat/sgm: Remove redundant platform_oid.h
This file is used when building the cert_create tool without using the 'standard' set of Arm OID values as defined in the TBBR specification (see tbbr_oid.h). This configuration is enabled by setting USE_TBBR_DEFS to 0 during build.
At the moment this will fail because the header file included by this file was removed in commit bb41eb7a9dc3 ("cert: move platform_oid.h to include/tools_share for all platforms"). For the SGM platform this means that there is no current use for this file.
Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| b028f2c5 | 22-Mar-2019 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-of
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
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| 7704ff91 | 22-Mar-2019 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume.
Reported by
rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume.
Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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| 4983f8b6 | 15-Mar-2019 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode.
This patch fixes the DBSC4 self-refresh mode sequen
rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode.
This patch fixes the DBSC4 self-refresh mode sequence.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com> Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
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| 285b6cfe | 11-Mar-2019 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-of
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
Update the revision number in the revision management file.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
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| 4988c4c1 | 01-Mar-2019 |
Chiaki Fujii <chiaki.fujii.wj@renesas.com> |
rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR] - Update DDR setting rev.0.35.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f
rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
[IPL/DDR] - Update DDR setting rev.0.35.
Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
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| d8e666a3 | 11-Mar-2019 |
Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> |
rcar_gen3: drivers: qos: change subslot cycle
Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252.
[IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver
rcar_gen3: drivers: qos: change subslot cycle
Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252.
[IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver.3.0 QoS setting rev.0.11. - Update M3 Ver.1.1 QoS setting rev.0.19. - Update M3 Ver.3.0 QoS setting rev.0.02. - Update M3N Ver.1.1 QoS setting rev.0.09.
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
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| 8c715587 | 11-Mar-2019 |
Yusuke Goda <yusuke.goda.sx@renesas.com> |
rcar_gen3: drivers: board: Add new board revision for H3ULCB
Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New]
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Cha
rcar_gen3: drivers: board: Add new board revision for H3ULCB
Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New]
Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
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| 11d15c3e | 11-Mar-2019 |
Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> |
rcar_gen3: plat: Change periodic write DQ training option.
Periodic write DQ training available as default.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yo
rcar_gen3: plat: Change periodic write DQ training option.
Periodic write DQ training available as default.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
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| 523ab5be | 08-Apr-2019 |
Clément Péron <peron.clem@gmail.com> |
plat: allwinner: common: use r_wdog instead of wdog
Some Allwinner H6 has a broken watchdog that doesn't make the soc reboot.
Use the R_WATCHDOG instead.
Signed-off-by: Clément Péron <peron.clem@g
plat: allwinner: common: use r_wdog instead of wdog
Some Allwinner H6 has a broken watchdog that doesn't make the soc reboot.
Use the R_WATCHDOG instead.
Signed-off-by: Clément Péron <peron.clem@gmail.com> Change-Id: Ie95cc30a80ed517b60b30d6bc2e655a1b53f18ba
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| 7d76df7d | 07-Apr-2019 |
Wei Yu <yuwei3@hisilicon.com> |
hikey960: Fix race condition between hotplug and idles
From the hotplug testing on Hikey960, in some case cores fail to become online in the system. When some cores are hotplugged off, if other core
hikey960: Fix race condition between hotplug and idles
From the hotplug testing on Hikey960, in some case cores fail to become online in the system. When some cores are hotplugged off, if other cores in the same cluster enter into CPU idle states at the meantime, the cluster will be powered off. This introduces the state machine malfunction in the power controller, thus when hotplug on the core afterwards, it fails to boot up the core because the power controller thinks the cluster is powered on.
This patch is to avoid race condition between hotplug and idles by preventing cluster power off when some of cores in the cluster are hotplugged off, if all cores in the same cluster are hotplugged off, the cluster can be powered off.
Change-Id: Ib2feeb093357c70409a3536cb4f9da9b504fdcbe Signed-off-by: Wei Yu <yuwei3@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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| c554e1ad | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
cache_helpers.s:fix mixed tabs and spaces
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> |
| f999faca | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruct
Add note about erratum 814220 for A7
On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added.
Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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| a738e155 | 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "aarch32: Allow compiling with soft-float toolchain" into integration |
| dbf65238 | 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "services/spm: Fix service UUID lookup" into integration |
| 72562aab | 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "cpus: Fix Cortex-A12 MIDR mask" into integration |
| 00e51ca3 | 08-Apr-2019 |
Paul Beesley <paul.beesley@arm.com> |
services/spm: Fix service UUID lookup
The spm_sp_get_by_uuid() function is used to look up the secure partition that provides a given service.
Within this function, memcmp() is used to compare the
services/spm: Fix service UUID lookup
The spm_sp_get_by_uuid() function is used to look up the secure partition that provides a given service.
Within this function, memcmp() is used to compare the service UUIDs but it uses the size of the rdsvc->uuid pointer instead of the size of its content (missing dereference). This means that only a partial comparison is performed as UUIDs are 128 bits in length and rdsvc->uuid is a uint32_t typed pointer.
Instead, use the size of the array pointed to by the svc_uuid parameter, which will be the full 128 bits, for the comparison.
Change-Id: I258fb0cca3bf19f97b8f2a4c133981647cd050e4 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 01e7e0ca | 09-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Add support for Cortex-A76AE CPU" into integration |
| 7a246d64 | 09-Apr-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Checkpatch: Style fix
Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> |
| 999adb94 | 08-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge changes from topic "jh/cotdesc" into integration
* changes: Document changes to auth-framework cot-desc: optimise memory further Reduce memory needed for CoT description |
| 9ccc5a57 | 04-Apr-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> |
| 699475ac | 22-Feb-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Document changes to auth-framework
The data structures in the auth-framework were changed by the previous patch, and need to be updated.
Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9 Signed-
Document changes to auth-framework
The data structures in the auth-framework were changed by the previous patch, and need to be updated.
Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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| 30070427 | 11-Mar-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
cot-desc: optimise memory further
This changes the auth_img_desc_t struct to have pointers to struct arrays instead of struct arrays. This saves memory as many of these were never used, and can be N
cot-desc: optimise memory further
This changes the auth_img_desc_t struct to have pointers to struct arrays instead of struct arrays. This saves memory as many of these were never used, and can be NULL pointers. Note the memory savings are only when these arrays are not initialised, as it is assumed these arrays are fixed length. A possible future optimisation could allow for variable length.
memory diff: bl1: bl2: text text -12 -12 bss bss -1463 0 data data -56 -48 rodata rodata -5688 -2592 total total -7419 -2652
Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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| 0b6377d1 | 20-Feb-2019 |
Joel Hutton <Joel.Hutton@Arm.com> |
Reduce memory needed for CoT description
When Trusted Board Boot is enabled, we need to specify the Chain of Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array of image descriptors. T
Reduce memory needed for CoT description
When Trusted Board Boot is enabled, we need to specify the Chain of Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array of image descriptors. The authentication module assumes that each image descriptor in this array is indexed by its unique image identifier. For example, the Trusted Boot Firmware Certificate has to be at index [TRUSTED_BOOT_FW_CERT_ID].
Unique image identifiers may not necessarily be consecutive. Also, a given BL image might not use all image descriptors. For example, BL1 does not need any of the descriptors related to BL31. As a result, the CoT array might contain holes, which unnecessarily takes up space in the BL binary.
Using pointers to auth_img_desc_t structs (rather than structs themselves) means these unused elements only use 1 pointer worth of space, rather than one struct worth of space. This patch also changes the code which accesses this array to reflect the change to pointers.
Image descriptors not needed in BL1 or BL2 respectively are also ifdef'd out in this patch. For example, verifying the BL31 image is the responsibility of BL2 so BL1 does not need any of the data structures describing BL31.
memory diff: bl1: bl2: text text -20 -20 bss bss -1463 0 data data -256 -48 rodata rodata -5240 -1952 total total -6979 -2020
Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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| 05c6693e | 08-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge "Fix restoration of PAuth context" into integration |