Update maintainers list

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <joh

Update maintainers list

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "doc: Document E and W build options" into integration

Merge changes from topic "jts/ti_fix" into integration

* changes:
ti: k3: common: Remove coherency workaround for AM65x
ti: k3: common: Use coherent memory for shared data

Merge "PSCI: Lookup list of parent nodes to lock only once" into integration

Merge "Update Allwinner SoC names in documentation" into integration

allwinner: Disable unused features to save space

As all Allwinner platforms are single-cluster A53 chips, we can disable
support for newer, unsupported architecture extensions. We can also
avoid som

allwinner: Disable unused features to save space

As all Allwinner platforms are single-cluster A53 chips, we can disable
support for newer, unsupported architecture extensions. We can also
avoid some cache maintenance code, since no platform-specific setup is
required to enable coherency.

These changes reduce the size of .text on a default build with GCC 9.1
enough that .vectors again fits in the second half of a page, instead
of requiring its own page.

This commit was boot-tested on the Pinebook.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d

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Update Allwinner SoC names in documentation

Provide the friendly marketing names, not just the platform name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id4427abb73d0c1be4ac1709

Update Allwinner SoC names in documentation

Provide the friendly marketing names, not just the platform name.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id4427abb73d0c1be4ac1709b2a8e87beffc20dd5

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Merge "Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703" into integration

PSCI: Lookup list of parent nodes to lock only once

When acquiring or releasing the power domain locks for a given CPU the
parent nodes are looked up by walking the up the PD tree list on both the
a

PSCI: Lookup list of parent nodes to lock only once

When acquiring or releasing the power domain locks for a given CPU the
parent nodes are looked up by walking the up the PD tree list on both the
acquire and release path, only one set of lookups is needed. Fetch the
parent nodes first and pass this list into both the acquire and release
functions to avoid the double lookup.

This also allows us to not have to do this lookup after coherency has
been exited during the core power down sequence. The shared struct
psci_cpu_pd_nodes is not placed in coherent memory like is done
for psci_non_cpu_pd_nodes and doing so would negatively affect
performance. With this patch we remove the need to have it in coherent
memory by moving the access out of psci_release_pwr_domain_locks().

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I7b9cfa9d31148dea0f5e21091c8b45ef7fe4c4ab

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Merge "FVP: Remove GIC initialisation from secondary core cold boot" into integration

Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703

Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaro

Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703

Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html

Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "Introduce BTI support in ROMLIB" into integration

ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the las

ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>

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ti: k3: common: Use coherent memory for shared data

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets

ti: k3: common: Use coherent memory for shared data

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>

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mediatek: mt8183: add mcsi driver

add mcsi driver to support cache coherence.

Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a
Signed-off-by: kenny liang <kenny.liang@mediatek.com>

mediatek: mt8183: add GIC driver

Add Mediatek GIC driver to support interrupt functions.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9

doc: Document E and W build options

Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

FVP: Remove GIC initialisation from secondary core cold boot

During the secondary cores' cold boot path, the cores initialise the GIC
CPU interface. However this is a redundant action since 1) the c

FVP: Remove GIC initialisation from secondary core cold boot

During the secondary cores' cold boot path, the cores initialise the GIC
CPU interface. However this is a redundant action since 1) the cores are
powered down immediately after that, 2) the GIC CPU interface is
initialised from scratch when the secondary cores are powered up again
later.

Moreover, this part of code was introducing a bug. In a GICv3 system,
the GIC's CPU interface system registers must not be written without the
core being marked as "awake" in the redistributor. However, this
sequence was performing such accesses and this would cause those cores
to hang. The hang was caused by the DSB instruction that would never
complete because of the GIC not recognising those writes.

For the two aforementioned reasons, the entire part of the GIC CPU
interface initialisation is removed.

Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "Apply compile-time check for AArch64-only cores" into integration

Merge "Prevent pending G1S interrupt become G0 interrupt" into integration

Prevent pending G1S interrupt become G0 interrupt

According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:

Prevent pending G1S interrupt become G0 interrupt

According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
- The PE does not implement EL3.
- ICC_SRE_EL1(S).SRE == 0

When a cpu enter suspend or deep idle, it might be
powered off. When the cpu resume, according to
the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and
9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if
write is allowed) and G0/G1S/G1NS interrupt of the
GIC cpu interface are all disabled.

If a G1S SPI interrupt occurred and the target cpu
of the SPI is assigned to a specific cpu which is
in suspend and is powered off, when the cpu resume
and start to initial the GIC cpu interface, the
initial sequence might affect the interrupt group
type of the pending interrupt on the cpu interface.

Current initial sequence on the cpu interface is:
1. Enable G0 interrupt
2. Enable G1S interrupt
3. Enable ICC_SRE_EL1(S).SRE

It is possible to treat the pending G1S interrupt
as G0 interrupt on the cpu interface if the G1S
SPI interrupt occurred between step2 and step3.

To prevent the above situation happend, the initial
sequence should be changed as follows:
1. Enable ICC_SRE_EL1(S).SRE
2. Enable G0 interrupt
3. Enable G1S interrupt

Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0
Signed-off-by: James Kung <kong1191@gmail.com>

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Apply compile-time check for AArch64-only cores

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is suppose

Apply compile-time check for AArch64-only cores

Some cores support only AArch64 mode. In those cores, only a limited
subset of the AArch32 system registers are implemented. Hence, if TF-A
is supposed to run on AArch64-only cores, it must be compiled with
CTX_INCLUDE_AARCH32_REGS=0.

Currently, the default settings for compiling TF-A are with the AArch32
system registers included. So, if we compile TF-A the default way and
attempt to run it on an AArch64-only core, we only get a runtime panic.

Now a compile-time check has been added to ensure that this flag has the
appropriate value when AArch64-only cores are included in the build.

Change-Id: I298ec550037fafc9347baafb056926d149197d4c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "doc: Enable automatic labels for page titles" into integration

Merge "Add information about the mailing list in the docs" into integration

Add information about the mailing list in the docs

Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>