Merge changes from topic "gby/cryptocell-multi-vers" into integration

* changes:
cryptocell: add product version awareness support
cryptocell: move Cryptocell specific API into driver

rockchip: px30: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Ena

rockchip: px30: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Only the actual errors are being tackled by this patch. It is up to the
platform to choose whether there needs to be further modifications to
the code.

Change-Id: I70860ae5f2a34d7c684bd491b76da50aa04f778e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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sgm775: Fix build fail for TSP support on sgm775

Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile

Change-Id: I89565127c67eff510e48e21fd450af4c3088c

sgm775: Fix build fail for TSP support on sgm775

Fixed the path to a source file specified in tsp makefile
Created a platform specific tsp makefile

Change-Id: I89565127c67eff510e48e21fd450af4c3088c2d4
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "Romlib makefile refactoring and script rewriting" into integration

cryptocell: add product version awareness support

Add support for multiple Cryptocell revisions which
use different APIs.

This commit only refactors the existing code in preperation to the addition

cryptocell: add product version awareness support

Add support for multiple Cryptocell revisions which
use different APIs.

This commit only refactors the existing code in preperation to the addition
of another Cryptocell revisions later on.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I16d80b31afb6edd56dc645fee5ea619cc74f09b6

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cryptocell: move Cryptocell specific API into driver

Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driv

cryptocell: move Cryptocell specific API into driver

Code using Cryptocell specific APIs was used as part of the
arm common board ROT support, instead of being abstracted
in Cryptocell specific driver code, creating two problems:
- Any none arm board that uses Cryptocell wuld need to
copy and paste the same code.
- Inability to cleanly support multiple versions of Cryptocell
API and products.

Move over Cryptocell specific API calls into the Cryptocell
driver, creating abstraction API where needed.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I9e03ddce90fcc47cfdc747098bece86dbd11c58e

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Merge changes from topic "jts/spsr" into integration

* changes:
Refactor SPSR initialisation code
SSBS: init SPSR register with default SSBS value

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_

Merge changes I0d17ba6c,I540741d2,I9e6475ad,Ifd769320,I12c04a85, ... into integration

* changes:
plat/mediatek/mt81*: Use new bl31_params_parse() helper
plat/rockchip: Use new bl31_params_parse_helper()
Add helper to parse BL31 parameters (both versions)
Factor out cross-BL API into export headers suitable for 3rd party code
Use explicit-width data types in AAPCS parameter structs
plat/rockchip: Switch to use new common BL aux parameter library
Introduce lightweight BL platform parameter library

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plat/mediatek/mt81*: Use new bl31_params_parse() helper

The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow

plat/mediatek/mt81*: Use new bl31_params_parse() helper

The Mediatek MT8173/MT8183 SoCs are prime candidates for switching to
the new bl31_params_parse() helper, so switch them over. This will allow
BL2 implementations on these platforms to transparently switch over to
the version 2 parameter structure.

Change-Id: I0d17ba6c455102d325a06503d2078a76d12b5deb
Signed-off-by: Julius Werner <jwerner@chromium.org>

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plat/rockchip: Use new bl31_params_parse_helper()

The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementatio

plat/rockchip: Use new bl31_params_parse_helper()

The Rockchip platform is a prime candidate for switching to the new
bl31_params_parse_helper(), so switch it over. This will allow BL2
implementations on this platform to transparently switch over to the
version 2 parameter structure.

Change-Id: I540741d2425c93f66c8697ce749a351eb2b3a7e8
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Merge "plat: imx8m: Add basic rdc module init driver" into integration

Merge "rockchip: px30: support px30" into integration

Refactor SPSR initialisation code

Change-Id: Ic3b30de13e314efca30fc71370227d3e76f1148b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

SSBS: init SPSR register with default SSBS value

This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we e

SSBS: init SPSR register with default SSBS value

This patch introduces an additional precautionary step to further
enhance protection against variant 4. During the context initialisation
before we enter the various BL stages, the SPSR.SSBS bit is explicitly
set to zero. As such, speculative loads/stores are by default disabled
for all BL stages when they start executing. Subsequently, each BL
stage, can choose to enable speculative loads/stores or keep them
disabled.

This change doesn't affect the initial execution context of BL33 which
is totally platform dependent and, thus, it is intentionally left up to
each platform to initialise.

For Arm platforms, SPSR.SSBS is set to zero for BL33 too. This means
that, for Arm platforms, all BL stages start with speculative
loads/stores disabled.

Change-Id: Ie47d39c391d3f20fc2852fc59dbd336f8cacdd6c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

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Merge "intel: agilex: Fix build error" into integration

intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enab

intel: agilex: Fix build error

"result of '1 << 31' requires 33 bits to represent, but 'int' only has
32 bits [-Werror=shift-overflow=]"

This is treated as an error since commit 93c690eba8ca ("Enable
-Wshift-overflow=2 to check for undefined shift behavior")

Change-Id: I141827a6711ab7759bfd6357e4ed9c1176da7c7b
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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Add helper to parse BL31 parameters (both versions)

BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit 726002263 (Add new version of image
l

Add helper to parse BL31 parameters (both versions)

BL31 used to take a single bl31_params_t parameter structure with entry
point information in arg0. In commit 726002263 (Add new version of image
loading.) this API was changed to a more flexible linked list approach,
and the old parameter structure was copied into all platforms that still
used the old format. This duplicated code unnecessarily among all these
platforms.

This patch adds a helper function that platforms can optionally link to
outsource the task of interpreting arg0. Many platforms are just
interested in the BL32 and BL33 entry point information anyway. Since
some platforms still need to support the old version 1 parameters, the
helper will support both formats when ERROR_DEPRECATED == 0. This allows
those platforms to drop a bunch of boilerplate code and asynchronously
update their BL2 implementation to the newer format.

Change-Id: I9e6475adb1a7d4bccea666118bd1c54962e9fc38
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-

Factor out cross-BL API into export headers suitable for 3rd party code

This patch adds a new include/export/ directory meant for inclusion in
third-party code. This is useful for cases where third-party code needs
to interact with TF-A interfaces and data structures (such as a custom
BL2-implementation like coreboot handing off to BL31). Directly
including headers from the TF-A repository avoids having to duplicate
all these definitions (and risk them going stale), but with the current
header structure this is not possible because handoff API definitions
are too deeply intertwined with other TF code/headers and chain-include
other headers that will not be available in the other environment.

The new approach aims to solve this by separating only the parts that
are really needed into these special headers that are self-contained and
will not chain-include other (non-export) headers. TF-A code should
never include them directly but should instead always include the
respective wrapper header, which will include the required prerequisites
(like <stdint.h>) before including the export header. Third-party code
can include the export headers via its own wrappers that make sure the
necessary definitions are available in whatever way that environment can
provide them.

Change-Id: Ifd769320ba51371439a8e5dd5b79c2516c3b43ab
Signed-off-by: Julius Werner <jwerner@chromium.org>

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Use explicit-width data types in AAPCS parameter structs

It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depend

Use explicit-width data types in AAPCS parameter structs

It's not a good idea to use u_register_t for the members of
aapcs64_params_t and aapcs32_params_t, since the width of that type
always depends on the current execution environment. This would cause
problems if e.g. we used this structure to set up the entry point of an
AArch32 program from within an AArch64 program. (It doesn't seem like
any code is doing that today, but it's probably still a good idea to
write this defensively. Also, it helps with my next patch.)

Change-Id: I12c04a85611f2b6702589f3362bea3e6a7c9f776
Signed-off-by: Julius Werner <jwerner@chromium.org>

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plat/rockchip: Switch to use new common BL aux parameter library

This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly sp

plat/rockchip: Switch to use new common BL aux parameter library

This patch changes all Rockchip platforms to use the new common BL aux
parameter helpers. Since the parameter space is now cleanly split in
generic and vendor-specific parameters and the COREBOOT_TABLE
parameter is now generic, the parameter type number for that parameter
has to change. Since it only affects coreboot which always builds TF as
a submodule and includes its headers directly to get these constants,
this should not cause any issues. In general, after this point, we
should avoid changing already assigned parameter type numbers whenever
possible.

Change-Id: Ic99ddd1e91ff5e5fe212fa30c793a0b8394c9dad
Signed-off-by: Julius Werner <jwerner@chromium.org>

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plat: imx8m: Add basic rdc module init driver

Add the basic support for RDC init/config driver,
this module driver can be enhanced more if necessary.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Cha

plat: imx8m: Add basic rdc module init driver

Add the basic support for RDC init/config driver,
this module driver can be enhanced more if necessary.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I290dc378d0d85671435f9de46d5aa790b4e006c8

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Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration

Merge "arm: Shorten the Firmware Update (FWU) process" into integration

Merge "Fix BL31 crash reporting on AArch64 only machines" into integration

n1sdp: fix DMC ECC enablement sequence in N1SDP platform

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This pa

n1sdp: fix DMC ECC enablement sequence in N1SDP platform

The DMC-620 memory controllers in N1SDP platform has to be put
into CONFIG state before writing to ERR0CTLR0 register to enable
ECC.

This patch fixes the sequence so that DMCs are set to CONFIG
state before writing to ERR0CTLR0 register and moved back to
READY state after writing.

Change-Id: I1252f3ae0991603bb29234029cddb5fbf869c1b2
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>

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