| f906a44e | 26-Jul-2019 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
libc: fix sparse warning for __assert()
Sparse warns this:
lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - di
libc: fix sparse warning for __assert()
Sparse warns this:
lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers
Add __dead2 to match the header declaration and C definition.
I also changed '__dead2 void' to 'void __dead2' for the consistency
with other parts.
Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| 705bed5d | 27-Aug-2019 |
Jolly Shah <jolly.shah@xilinx.com> |
plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()
Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initializ
plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()
Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initialization from sip_svc_setup() to zynqmp_config_setup().
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
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| ebf851ed | 04-Sep-2019 |
Yann Gautier <yann.gautier@st.com> |
stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CR
stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver
The STM32 console driver was pre-pending '\r' before '\n'.
It is now managed by the framework with the flag:
CONSOLE_FLAG_TRANSLATE_CRLF.
Remove the code in driver, and add the flag for STM32MP1.
Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 0289ab9e | 10-Sep-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1:
Merge changes from topic "yg/stm32mp1_wdg_updates" into integration
* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support
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| 40b06510 | 27-Aug-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Add python configuration for editorconfig
As it currently is, python files are formatted using the general rules
in .editorconfig - this means that 8-character hard tabs are used, which
is not the r
Add python configuration for editorconfig
As it currently is, python files are formatted using the general rules
in .editorconfig - this means that 8-character hard tabs are used, which
is not the recommended behaviour according to the PEP-8 standard. This
patch correct this, and additionally limits the line length to 79
characters as required by the standard.
Change-Id: I3b5c0aff12034c4184d4555aab36490cdb3885da
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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| 0d8cb493 | 02-May-2019 |
Hung-Te Lin <hungte@chromium.org> |
mediatek: mt8183: Support coreboot configuration
When built for coreboot, we want to enable coreboot library to have
better integration. For example, serial console should be initialized by
coreboot
mediatek: mt8183: Support coreboot configuration
When built for coreboot, we want to enable coreboot library to have
better integration. For example, serial console should be initialized by
coreboot_serial instead of hard-coded values.
Most coreboot configuration will enable memory console, which needs
larger XLAT_TABLES so MAX_XLAT_TABLES is increased; and to support that,
TZRAM_SIZE also need to be enlarged.
Change-Id: I08cf22df2fa26e48284e323d22ad8ce73a6ea803
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
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| 3d91c9c3 | 03-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: support system reset
Implement system reset handler.
Change-Id: I535ee414616dde8d2b59dec5a723a540a3a1341d
Signed-off-by: kenny liang <kenny.liang@mediatek.com> |
| a5612057 | 03-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: pass platform parameters
Add plat parameter structs to support BL2 to pass
variable-length, variable-type parameters to BL31.
The parameters are structured as a link list.
During B
mediatek: mt8183: pass platform parameters
Add plat parameter structs to support BL2 to pass
variable-length, variable-type parameters to BL31.
The parameters are structured as a link list.
During BL31 setup time, we traverse the list to process
each parameter.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: Ie84cfc9606656fb1d2780a68cadf27e09afa6628
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|
| 50cd9522 | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: add GPIO driver
Add GPIO driver.
Change-Id: I8c35ce4ea247f3726081b0bbb95f0930c2b82517
Signed-off-by: kenny liang <kenny.liang@mediatek.com> |
| e977b4db | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: support system off
- Add PMIC driver
- Add RTC drvier
- Refactor PMIC and RTC to mediatek/common
- Implement system off handler
Change-Id: If76497646ace1b78bc9a5fa0110b652fe512281
mediatek: mt8183: support system off
- Add PMIC driver
- Add RTC drvier
- Refactor PMIC and RTC to mediatek/common
- Implement system off handler
Change-Id: If76497646ace1b78bc9a5fa0110b652fe512281a
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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|
| 7352f329 | 02-May-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: support CPU hotplug
- Add DCM driver
- Add SPMC driver
- Implement core and cluster power on/off handlers
Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72
Signed-off-by: kenny
mediatek: mt8183: support CPU hotplug
- Add DCM driver
- Add SPMC driver
- Implement core and cluster power on/off handlers
Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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|
| f992b960 | 25-Jun-2019 |
kenny liang <kenny.liang@mediatek.com> |
mediatek: mt8183: refine GIC driver
Refine MTK GIC driver.
Remove unused codes.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I39e05ce7aa3c257e237fbc8e661cdde65cbcec7c |
| 0c411c78 | 16-Aug-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Assert if power level value greater then PSCI_INVALID_PWR_LVL
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I4a496d5a8e7a9a127cd6224c968539eb74932fca |
| 88d493fb | 18-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Add documentation for CTX_INCLUDE_MTE_REGS
A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds
documentation for it in the User Guide along with instructions of what
different va
Add documentation for CTX_INCLUDE_MTE_REGS
A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds
documentation for it in the User Guide along with instructions of what
different values mean.
Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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|
| 9dd94382 | 18-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Enable MTE support in both secure and non-secure worlds
This patch adds support for the new Memory Tagging Extension arriving in
ARMv8.5. MTE support is now enabled by default on systems that suppor
Enable MTE support in both secure and non-secure worlds
This patch adds support for the new Memory Tagging Extension arriving in
ARMv8.5. MTE support is now enabled by default on systems that support
at EL0. To enable it at ELx for both the non-secure and the secure
world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving
and restoring when necessary in order to prevent register leakage
between the worlds.
Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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|
| 1946b868 | 08-Aug-2019 |
Imre Kis <imre.kis@arm.com> |
Add Linux DTS files for 32 bit threaded FVPs
RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file co
Add Linux DTS files for 32 bit threaded FVPs
RevC models have the MT bit set and the affinities shifted in the MPIDR
register. To make the Linux able to boot all CPUs it needs a modified
DTS file containing the shifted affinity values.
Beside these values the DTS files should be the same so the common part
was moved into a new file which is included in the DTS files with
shifted and non-shifted affinities.
The same setup already exists for 64 bit systems.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: I90f7b9c8d8a24c9b3f97232441dbe0a29aa8976d
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|
| 36bf55d6 | 05-Sep-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: fix "overflow before widen" coverity issue
This patch fixes a coding error, where the size of the protected memory area
was truncated due to an incorrect typecast.
This defect wa
Tegra: memctrl_v2: fix "overflow before widen" coverity issue
This patch fixes a coding error, where the size of the protected memory area
was truncated due to an incorrect typecast.
This defect was found by coverity and reported as CID 336781.
Change-Id: I41878b0a9a5e5cd78ef3393fdc7b9ea7f7403ed3
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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|
| 9158854a | 28-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the SoC specific files
Remove the GXBB prefix where needed and add SoC specific prefixes for
GXBB/GXL.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic3eb3a
amlogic: Fix prefixes in the SoC specific files
Remove the GXBB prefix where needed and add SoC specific prefixes for
GXBB/GXL.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27
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|
| 0e1d7896 | 28-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the PM code
Remove the GXBB prefix from the code in the common directory and add
SoC-specific prefixes in the SoC specific code.
Signed-off-by: Carlo Caione <ccaione@baylib
amlogic: Fix prefixes in the PM code
Remove the GXBB prefix from the code in the common directory and add
SoC-specific prefixes in the SoC specific code.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030
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|
| 9a5616fa | 28-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the SCPI related code
Add a new aml_* prefix to the SCPI related function calls.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I697812ac1c0df28cbb639a1dc3e8
amlogic: Fix prefixes in the SCPI related code
Add a new aml_* prefix to the SCPI related function calls.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739
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|
| cbaad533 | 28-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the MHU code
Make the MHU code AML specific adding a new aml_* prefix and remove the
GXBB prefix from the register names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
amlogic: Fix prefixes in the MHU code
Make the MHU code AML specific adding a new aml_* prefix and remove the
GXBB prefix from the register names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2
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|
| 381b901f | 26-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the SIP/SVC code
All the SIP/SVC related code is currently the same between GXL and GXBB.
Rename function names and register names to avoid hardcoding the GXBB
prefix.
Sign
amlogic: Fix prefixes in the SIP/SVC code
All the SIP/SVC related code is currently the same between GXL and GXBB.
Rename function names and register names to avoid hardcoding the GXBB
prefix.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf
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|
| 73f6d057 | 25-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the thermal driver
No need to have a special SoC-specific prefix.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59 |
| 010fdc1b | 25-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the private header file
The header file is shared between all the SoCs. Better avoiding
hardcoding the SoC name in the function names.
Signed-off-by: Carlo Caione <ccaione@
amlogic: Fix prefixes in the private header file
The header file is shared between all the SoCs. Better avoiding
hardcoding the SoC name in the function names.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I9074871bd1ed8a702c1a656e0f50f2d3c6cb0425
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|
| 93c795ae | 25-Aug-2019 |
Carlo Caione <ccaione@baylibre.com> |
amlogic: Fix prefixes in the efuse driver
The efuse driver is hardcoding the GXBB prefix. No need to do that since
the driver is shared between multiple SoCs.
Signed-off-by: Carlo Caione <ccaione@b
amlogic: Fix prefixes in the efuse driver
The efuse driver is hardcoding the GXBB prefix. No need to do that since
the driver is shared between multiple SoCs.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: I97691b0bbd55170d8216d301a3fc04feb8c2af2e
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