zynqmp: pm: Rename FPD WDT clock ID

This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <j

zynqmp: pm: Rename FPD WDT clock ID

This patch renames FPD WDT clock ID from CLK_WDT to CLK_FPD_WDT.

Signed-off-by: Mounika Grace Akula <mounika.grace.akula@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I4d00a59b1dc54920115a2da55e8a06347fe2231c

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plat: xilinx: zynqmp: Correct syscnt freq for QEMU

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jol

plat: xilinx: zynqmp: Correct syscnt freq for QEMU

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214

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arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values o

arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34

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arm64: zynqmp: Add id for new RFSoC device ZU39DR

This patch adds new RFSoC device ZU39DR to zynqmp
devices list

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-of

arm64: zynqmp: Add id for new RFSoC device ZU39DR

This patch adds new RFSoC device ZU39DR to zynqmp
devices list

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d

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Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration

FVP: Stop reclaiming init code with Clang builds

The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.

Change-Id: I993

FVP: Stop reclaiming init code with Clang builds

The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.

Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>

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A5DS: Change boot address to point to DDR address

Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR

Change

A5DS: Change boot address to point to DDR address

Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR

Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

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A5DS: Correct system freq, Cache Writeback Granule

Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeb

A5DS: Correct system freq, Cache Writeback Granule

Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback

Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

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Merge "GCC: Upgrade to version 9.2-2019.12 of toolchain" into integration

rcar_gen3: plat: Pass DT to OpTee OS

Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7d5ebae8d7

rcar_gen3: plat: Pass DT to OpTee OS

Pass DT to OpTee OS, so that OpTee OS can extract NSEC RAM layout from the DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7d5ebae8d7ab9c70f079e30563d66bbd6a8ac7a4

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rcar_gen3: drivers: ddr: Move DDR drivers out of staging

Now that DDR drivers are mostly cleaned up , move them out of staging.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id:

rcar_gen3: drivers: ddr: Move DDR drivers out of staging

Now that DDR drivers are mostly cleaned up , move them out of staging.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9de63f847a0ef9ac27a79fb0f848c351fd7f4da6

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Merge "drivers: add a driver for snoop control unit" into integration

drivers: add a driver for snoop control unit

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data c

drivers: add a driver for snoop control unit

The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.

The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.

Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.

This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT

Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>

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GCC: Upgrade to version 9.2-2019.12 of toolchain

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 ba

GCC: Upgrade to version 9.2-2019.12 of toolchain

This toolchain provides multiple cross compilers and are publicly
available on www.developer.arm.com

We thoroughly test TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I2360a3ac6705c68dca781b85e9894867df255b3e
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "bl31: Split into two separate memory regions" into integration

Merge "mediatek: mt8183: add Vmodem/Vcore DVS init level" into integration

compiler_rt: Import aeabi_ldivmode.S file and dependencies

Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the
LLVM compiler_rt library on master branch as of 30 Oct 2018
(SVN revision: r3

compiler_rt: Import aeabi_ldivmode.S file and dependencies

Import aeabi_ldivmod.S with divmoddi4.c and divdi3.c from the
LLVM compiler_rt library on master branch as of 30 Oct 2018
(SVN revision: r345645).

This is to get the __aeabi_ldivmod builtin, which is required
by a patch using signed long long division.

Change-Id: Iee4c421deb3175142655e19074cd3732edd82227
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Merge "allwinner: Remove unused include path" into integration

Merge "rockchip: rk3328: Enable workaround for erratum 855873" into integration

Merge "Workaround for Hercules erratum 1688305" into integration

plat: rpi4: Skip UART initialisation

So far we have seen two different clock setups for the Raspberry Pi 4
board, with the VPU clock divider being different. This was handled by
reading the divider

plat: rpi4: Skip UART initialisation

So far we have seen two different clock setups for the Raspberry Pi 4
board, with the VPU clock divider being different. This was handled by
reading the divider register and adjusting the base clock rate
accordingly.
Recently a new GPU firmware version appeared that changed the clock rate
*again*, though this time at a higher level, so the VPU rate (and the
apparent PLLC parent clock) did not seem to change, judging by reading
the clock registers.
So rather than playing cat and mouse with the GPU firmware or going
further down the rabbit hole of exploring the whole clock tree, let's
just skip the baud rate programming altogether. This works because the
GPU firmware actually sets up and programs the debug UART already, so
we can just use it.

Pass 0 as the base clock rate to let the console driver skip the setup,
also remove the no longer needed clock code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ica88a3f3c9c11059357c1e6dd8f7a4d9b1f98fd7

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console: 16550: Prepare for skipping initialisation

On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor

console: 16550: Prepare for skipping initialisation

On some platforms the UART might have already been initialised, for
instance by firmware running before TF-A or by a separate management
processor. In this case it would not be need to initialise it again
(doing so could create spurious characters). But more importantly this
saves us from knowing the right baudrate and the right base clock rate
for the UART. This can lead to more robust and versatile firmware builds.

Allow to skip the 16550 UART initialisation and baud rate divisor
programming, by interpreting an input clock rate of "0" to signify this
case. This will just skip the call to console_16550_core_init, but still
will register the console properly.

Users should just pass 0 as the second parameter, the baudrate (third
parameter) will then be ignored as well.

Fix copy & paste typos in comments for the console_16550_register()
function on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I9f8fca5b358f878fac0f31dc411358fd160786ee

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Merge "uniphier: run BL33 at EL2" into integration

intel: Fix memory calibration

Increase calibration delay to cater for HPS 1st mode and
reduce clear emif delay which takes too long

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@in

intel: Fix memory calibration

Increase calibration delay to cater for HPS 1st mode and
reduce clear emif delay which takes too long

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1a50a5d8a6518ba085d853cb636efa07326552b4

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intel: Implement platform specific system reset 2

Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for

intel: Implement platform specific system reset 2

Add support for platform specific warm-reset through psci system reset 2.

- system_reset2 implementation that calls for l2 cache reset
- Check for magic number and request for warm reset in bl2
- Create a shared reset manager header file for Agilex and Stratix 10
- Clean up parameter info in plat_get_next_bl_params

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726

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