Merge "doc: Split the User Guide into multiple files" into integration

doc: Split the User Guide into multiple files

The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information

doc: Split the User Guide into multiple files

The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information from. Currently, it covers
these topics and maybe a couple more:

- Requirements (hardware, tools, libs)
- Checking out the repo
- Basic build instructions
- A comprehensive list of build flags
- FIP packaging
- Building specifically for Juno
- Firmware update images
- EL3 payloads
- Preloaded BL33 boot flow
- Running on FVPs
- Running on Juno

I have separated these out into a few groups that become new
documents. Broadly speaking, build instructions for the tools,
for TF-A generally, and for specific scenarios are separated.
Content relating to specific platforms (Juno and the FVPs are
Arm-specific platforms, essentially) has been moved into the
documentation that is specific to those platforms, under
docs/plat/arm.

Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

show more ...

plat/st: Fix incorrect return value

Change the return code in boot_api.h which impacts the
authentication result.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I2c3aadb98dd261ae5

plat/st: Fix incorrect return value

Change the return code in boot_api.h which impacts the
authentication result.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I2c3aadb98dd261ae5ad73978fc74a8a8cfa59b82
Reviewed-by: Yann GAUTIER <yann.gautier@st.com>

show more ...

Changes to support updated register usage in SMCCC v1.2

From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch

Changes to support updated register usage in SMCCC v1.2

From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch32 state, arguments are passed in registers R0-R7 and
results are returned in registers R0-R7 for SMC32 calls.

Most of the functions and macros already existed to support using
upto 8 registers for passing/returning parameters/results. Added
few helper macros for SMC calls from AArch32 state.

Link to the specification:
https://developer.arm.com/docs/den0028/c

Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

adding support to enable different personality of the same soc.

Same SoC has different personality by creating different number of:
- cores
- clusters.

As a result, the platform specific power doma

adding support to enable different personality of the same soc.

Same SoC has different personality by creating different number of:
- cores
- clusters.

As a result, the platform specific power domain tree will be created
after identify the personality of the SoC.
Hence, platform specific power domain tree may not be same for all the
personality of the soc.

Thus, psci library code will deduce the 'plat_core_count', while
populating the power domain tree topology and return the number of
cores.

PLATFORM_CORE_COUNT will still be valid for a SoC, such that
psci_plat_core_count <= PLATFORM_CORE_COUNT.

PLATFORM_CORE_COUNT will continued to be defined by platform to create
the data structures.

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I1f5c47647631cae2dcdad540d64cf09757db7185

show more ...

allwinner: power: Add DLDO4 power rail

A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known

allwinner: power: Add DLDO4 power rail

A64-OLinuXino family boards (maybe others too) uses PG for USB vbus
enable/disable. However PG is supplied by DLDO4, which is not present
in the list of known regulators. This patch adds DLD04 to it.

Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Change-Id: I31d3bb3e0004ccf5b282d08b530ee44979da0466

show more ...

Merge changes I5693ad56,I9ddc077a into integration

* changes:
mediatek: mt8183: Fix AARCH64 init fail on CPU0
mediatek: mt8183: refine GIC driver for low power scenarios

Add memory_map tools as a target for Make

Create a new "memmap" target for the Makefile, which prints a
representation of the memory map for the build. The information are
extracted from the .map fi

Add memory_map tools as a target for Make

Create a new "memmap" target for the Makefile, which prints a
representation of the memory map for the build. The information are
extracted from the .map files by the "print_memory_map.py" tools.

Change-Id: Id5ebc7ce8a3a571c7ac4848be14657cf2fd711f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

tools: Add show_memory script

show_memory is a simple tools that parse the blx.map files and print a
representation of the memory layout for the latest build.
This representation is based on standar

tools: Add show_memory script

show_memory is a simple tools that parse the blx.map files and print a
representation of the memory layout for the latest build.
This representation is based on standard symbols present on the map
files as: __TEXT_START/END__, __RODATA_START/END__, __STACKS_START/END__
, etc..

Change-Id: Iba3e301a1a9fee9a35abf1afdb69093617d33929
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

mediatek: mt8183: Fix AARCH64 init fail on CPU0

CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race con

mediatek: mt8183: Fix AARCH64 init fail on CPU0

CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.

Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.

Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

show more ...

mediatek: mt8183: refine GIC driver for low power scenarios

Implement rdist save/resore functions to support low power scenarios.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9

mediatek: mt8183: refine GIC driver for low power scenarios

Implement rdist save/resore functions to support low power scenarios.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7

show more ...

Merge "mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM" into integration

Merge "Fix multithreaded FVP power domain tree" into integration

Merge "Add multithreaded DynamIQ dts file" into integration

Merge "GIC-600: Fix include ordering according to the coding style" into integration

Enable -Wlogical-op always

-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While t

Enable -Wlogical-op always

-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While these are perfectly valid behavior, they
can be a sign that something is slightly off.

This patch adds this warning to gcc and it's closest equivalent to
clang, while also fixing any warnings that enabling them causes.

Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

show more ...

Enable -Wshadow always

Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion

Enable -Wshadow always

Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion and can make refactoring and bug hunting
more difficult.

This patch moves -Wshadow from WARNING2 into the general warning group
so it is always used. It also fixes all warnings that this introduces
by simply renaming the local variable to a new name

Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

show more ...

Remove unnecessary warning options

Both -Wmissing-field-initializers and -Wsign-compare are both covered by
-Wextra which is enabled at W=1 anyway. Therefore, the explicit options
are not required.

Remove unnecessary warning options

Both -Wmissing-field-initializers and -Wsign-compare are both covered by
-Wextra which is enabled at W=1 anyway. Therefore, the explicit options
are not required.

Change-Id: I2e7d95b5fc14af7c70895859a7ebbeac5bc0d2a4
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

show more ...

Refactor the warning flags

This patch keeps the same warnings, and simply reorders them to keep all
the warning options together in one place.

Change-Id: Ibb655dcabc84f3af01a0d7f71f5af7e0479c2521
S

Refactor the warning flags

This patch keeps the same warnings, and simply reorders them to keep all
the warning options together in one place.

Change-Id: Ibb655dcabc84f3af01a0d7f71f5af7e0479c2521
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

show more ...

GIC-600: Fix include ordering according to the coding style

Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: remove L2 ECC parity protection setting
Tegra194: sip_calls: mark unused parameter as const
Tegra194: i

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: remove L2 ECC parity protection setting
Tegra194: sip_calls: mark unused parameter as const
Tegra194: implement handler to retrieve power domain tree
Tegra194: mce: fix function declaration conflicts
Tegra194: add macros to read GPU reset status
Tegra194: skip notifying MCE in fake system suspend
Tegra194: Enable system suspend

show more ...

Merge changes from topic "lm/improve_memory_layout" into integration

* changes:
DOC: Update ROMLIB page with memory impact info
ROMLIB: Optimize memory layout when ROMLIB is used

DOC: Update ROMLIB page with memory impact info

Complete the Library at ROM documentation with information regarding
the memory impact of the feature.

Change-Id: I5a10620a8e94f123021bb19523a36d558b

DOC: Update ROMLIB page with memory impact info

Complete the Library at ROM documentation with information regarding
the memory impact of the feature.

Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

ROMLIB: Optimize memory layout when ROMLIB is used

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this

ROMLIB: Optimize memory layout when ROMLIB is used

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

show more ...

Merge "Refactor load_auth_image_internal()." into integration