| 7bad6e08 | 15-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "allwinner: Reenable USE_COHERENT_MEM" into integration |
| 6c281cc3 | 27-Oct-2019 |
Samuel Holland <samuel@sholland.org> |
allwinner: Reenable USE_COHERENT_MEM
Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies
allwinner: Reenable USE_COHERENT_MEM
Now that there is plenty of space (32 KiB) available for NOBITS
sections, we can afford using an entire page for coherent memory. In
fact, because it simplifies the code, this is a beneficial change for
loaded image (.text) size, where we are still close to the size limit.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I0b899dabcb162015c63b0e4aed0869569c889ed9
show more ...
|
| 8c11ebfc | 13-Jan-2020 |
Luka Kovacic <luka.kovacic@sartura.hr> |
a8k: Implement platform specific power off
Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.
Marvell Armada 8K boards can now add a board/system_power.c file
a8k: Implement platform specific power off
Implements a way to add platform specific power off code to a
Marvell Armada 8K platform.
Marvell Armada 8K boards can now add a board/system_power.c file
that contains a system_power_off() function.
This function can now send a command to a power management MCU or
other board periferals before shutting the board down.
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: Iaba20bc2f603195679c54ad12c0c18962dd8e3db
---
I am working on a device that will be ported later, which has a
custom power management MCU that handles LEDs, board power and fans
and requires this separation.
show more ...
|
| 6be71b09 | 06-Jan-2020 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
rcar_gen3: Add missing #{address,size}-cells into generated DT
Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this corr
rcar_gen3: Add missing #{address,size}-cells into generated DT
Add missing #address-cells and #size-cells into generated DT, otherwise
the DT is invalid. While the parsers thus far handled this correctly via
various fallbacks, this is not applicable in the long run, so fix this.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic808a3b27b93e5258ec1a19acc3d593e53625c15
show more ...
|
| 5e07b700 | 19-Mar-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm_service: Add support to query max divisor
Add new QID to get maximum supported divisor by clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel
zynqmp: pm_service: Add support to query max divisor
Add new QID to get maximum supported divisor by clock.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a
show more ...
|
| 138cde66 | 15-Mar-2019 |
Ravi Patel <ravi.patel@xilinx.com> |
zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node
Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value t
zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node
Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b
show more ...
|
| 74cf2158 | 15-Mar-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm: clock: Move custom flags to typeflags
Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.
Signed-off-by: Rajan Va
zynqmp: pm: clock: Move custom flags to typeflags
Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78
show more ...
|
| 75b90fe8 | 15-Mar-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
zynqmp: pm: clock: Add support for custom type flags
Add support to add extra custom type flags and provide
to caller in topology query.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off
zynqmp: pm: clock: Add support for custom type flags
Add support to add extra custom type flags and provide
to caller in topology query.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40
show more ...
|
| b0eae6f9 | 04-Mar-2019 |
Rajan Vaja <rajan.vaja@xilinx.com> |
plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.
Signed-off-by: Rajan Vaja <rajan.vaja@xili
plat: xilinx: zynqmp: Add GET_CALLBACK_DATA function
Add GET_CALLBACK_DATA function again as now Linux driver
supports both mailbox as well as ISR method.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ieb99d61976e1cb718fcd1021d9cf4958e7556c81
show more ...
|
| e9ed7fa7 | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sip-svc" into integration
* changes:
intel: Implement platform specific system reset 2
intel: Enable SiP SMC secure register access |
| 4694e1e7 | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "uniphier: call uniphier_scp_is_running() only when on-chip STM is supported" into integration |
| bc3579b7 | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "intel: Fix memory calibration" into integration |
| f1c94d1e | 14-Jan-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "rpi4: Fix documentation of armstub config entry" into integration |
| 43309051 | 09-Dec-2019 |
Jan Kiszka <jan.kiszka@siemens.com> |
rpi4: Fix documentation of armstub config entry
It's in fact mandatory. Seen with RPi firmware 1.20190925.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26
rpi4: Fix documentation of armstub config entry
It's in fact mandatory. Seen with RPi firmware 1.20190925.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Change-Id: I80739b74f25817294adc52cfd26a3ec59c06f892
show more ...
|
| ba1eaabf | 07-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
cert_create: Remove some unused header files inclusions
The chain of trust definitions are only needed in the part of the code
dealing with the TBBR CoT (tbbr/* files).
Change-Id: I6f9a86bba4a2d163
cert_create: Remove some unused header files inclusions
The chain of trust definitions are only needed in the part of the code
dealing with the TBBR CoT (tbbr/* files).
Change-Id: I6f9a86bba4a2d16313b6842a3ec85b7c951074bc
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| 2aa60e70 | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "plat: rpi4: Skip UART initialisation" into integration |
| 22c2316d | 14-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "console: 16550: Prepare for skipping initialisation" into integration |
| 2049b6f9 | 14-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "add-versal-soc-support" into integration
* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
Merge changes from topic "add-versal-soc-support" into integration
* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
zynqmp: pm: Rename FPD WDT clock ID
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
arm64: zynqmp: Add id for new RFSoC device ZU39DR
show more ...
|
| 2d51b55e | 10-Jan-2020 |
Balint Dobszay <balint.dobszay@arm.com> |
Replace dts includes with C preprocessor syntax
Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. Th
Replace dts includes with C preprocessor syntax
Using the /include/ syntax, the include was evaluated by dtc, only after running
the preprocessor, therefore the .dtsi files were not preprocessed. This patch
adds the #include syntax instead. Evaluating this and preprocessing the files
now happens in a single step, done by the C preprocessor.
Change-Id: I6d0104b6274316fc736e84973502a4d6c2c9d6e0
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
show more ...
|
| f1f8ea20 | 14-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "allwinner: Move the NOBITS region to SRAM A1" into integration |
| 743600b2 | 13-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: Remove un-needed checks for qspi driver r/w" into integration |
| d5ce8df7 | 13-Jan-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "tegra-misra-21.1-fixes" into integration
* changes:
Tegra194: drivers: fix violations of MISRA Rule 21.1
Tegra: include: fix violations of MISRA Rule 21.1 |
| b52ff570 | 13-Jan-2020 |
Fathi Boudra <fathi.boudra@varian.com> |
Add a .gitreview file for convenience
Signed-off-by: Fathi Boudra <fathi.boudra@linaro.org>
Change-Id: I2683da5071466ba3c81f0bd6f3bf51163971feab |
| dadd8060 | 13-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "docs: GCC toolchain upgrade to version 9.2-2019.12" into integration |
| f6c4b19a | 13-Jan-2020 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Remove un-needed checks for qspi driver r/w
This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.
Signed-off-by: Hadi Asyrafi
intel: Remove un-needed checks for qspi driver r/w
This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53
show more ...
|