Merge changes from topic "ti-cluster-power" into integration

* changes:
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
ti: k3: drivers: ti_sci: Remove indirect structure of cons

Merge changes from topic "ti-cluster-power" into integration

* changes:
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
ti: k3: drivers: ti_sci: Remove indirect structure of const data
ti: k3: common: Enable ARM cluster power down
ti: k3: common: Rename device IDs to be more consistent

show more ...

Merge "plat/arm/sgi: move topology information to board folder" into integration

Merge "Tegra194: enable spe-console functionality" into integration

Tegra194: enable spe-console functionality

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: V

Tegra194: enable spe-console functionality

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

show more ...

Merge "Neovers N1: added support to update presence of External LLC" into integration

plat/arm: Add support for SEPARATE_NOBITS_REGION

In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence m

plat/arm: Add support for SEPARATE_NOBITS_REGION

In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.

Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.

Memory map for BL31 NOBITS region also has to be created.

Change-Id: Ibbc8c9499a32e63fd0957a6e254608fbf6fa90c9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes a

Changes necessary to support SEPARATE_NOBITS_REGION feature

Since BL31 PROGBITS and BL31 NOBITS sections are going to be
in non-adjacent memory regions, potentially far from each other,
some fixes are needed to support it completely.

1. adr instruction only allows computing the effective address
of a location only within 1MB range of the PC. However, adrp
instruction together with an add permits position independent
address of any location with 4GB range of PC.

2. Since BL31 _RW_END_ marks the end of BL31 image, care must be
taken that it is aligned to page size since we map this memory
region in BL31 using xlat_v2 lib utils which mandate alignment of
image size to page granularity.

Change-Id: I3451cc030d03cb2032db3cc088f0c0e2c84bffda
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

ti: k3: drivers: ti_sci: Put sequence number in coherent memory

The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so ac

ti: k3: drivers: ti_sci: Put sequence number in coherent memory

The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807

show more ...

ti: k3: drivers: ti_sci: Remove indirect structure of const data

The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
str

ti: k3: drivers: ti_sci: Remove indirect structure of const data

The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072

show more ...

ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sendi

ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216

show more ...

ti: k3: common: Rename device IDs to be more consistent

The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

ti: k3: common: Rename device IDs to be more consistent

The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59

show more ...

T589: Fix insufficient ordering guarantees in bakery lock

bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient i

T589: Fix insufficient ordering guarantees in bakery lock

bakery_lock_get() uses DMB LD after lock acquisition and
bakery_lock_release() uses DMB ST before releasing the lock. This is
insufficient in both cases. With just DMB LD, stores in the critical
section can be reordered before the DMB LD which could mean writes in
the critical section completing before the lock has been acquired
successfully. Similarly, with just DMB ST, a load in the critical section
could be reordered after the the DMB ST. DMB is the least expensive
barrier that can provide the required ordering.

Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
Change-Id: Ieb74cbf5b76b09e1789331b71f37f7c660221b0e

show more ...

Merge changes from topic "pie" into integration

* changes:
uniphier: make all BL images completely position-independent
uniphier: make uniphier_mmap_setup() work with PIE
uniphier: pass SCP ba

Merge changes from topic "pie" into integration

* changes:
uniphier: make all BL images completely position-independent
uniphier: make uniphier_mmap_setup() work with PIE
uniphier: pass SCP base address as a function parameter
uniphier: set buffer offset and length for io_block dynamically
uniphier: use more mmap_add_dynamic_region() for loading images
bl_common: add BL_END macro
uniphier: turn on ENABLE_PIE
TSP: add PIE support
BL2_AT_EL3: add PIE support
BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work
PIE: pass PIE options only to BL31
Build: support per-BL LDFLAGS

show more ...

Neovers N1: added support to update presence of External LLC

CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal L

Neovers N1: added support to update presence of External LLC

CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.

To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363

show more ...

plat/arm/sgi: move topology information to board folder

The platform topology description of the upcoming Arm's RD platforms
have different topology than those listed in the sgi_topology.c file. So

plat/arm/sgi: move topology information to board folder

The platform topology description of the upcoming Arm's RD platforms
have different topology than those listed in the sgi_topology.c file. So
instead of adding platform specific topology into existing
sgi_topology.c file, those can be added to respective board files. In
order to maintain consistency with the upcoming platforms, move the
existing platform topology description to respective board files.

Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

show more ...

Merge "plat/sgm: Always use SCMI for SGM platforms" into integration

Merge "xilinx: Unify Platform specific defines for PSCI module" into integration

plat/sgm: Always use SCMI for SGM platforms

As on SGI platforms, SCPI is unsupported on SGM platforms.

Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.c

plat/sgm: Always use SCMI for SGM platforms

As on SGI platforms, SCPI is unsupported on SGM platforms.

Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

xilinx: Unify Platform specific defines for PSCI module

PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_

xilinx: Unify Platform specific defines for PSCI module

PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b

show more ...

uniphier: make all BL images completely position-independent

This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.

The

uniphier: make all BL images completely position-independent

This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.

The ENABLE_PIE improves the maintainability and usability. You can reuse
a single set of BL images for other SoC/board without re-compiling TF-A
at all. This will also keep the code cleaner because it avoids #ifdef
around various base addresses.

By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really
position-independent now. You can load them anywhere irrespective of
their link address.

Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

uniphier: make uniphier_mmap_setup() work with PIE

BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h,
that is, determined at link-time.

On the other hand, BL2_END, BL31_END, and BL32

uniphier: make uniphier_mmap_setup() work with PIE

BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h,
that is, determined at link-time.

On the other hand, BL2_END, BL31_END, and BL32_END are derived from
the symbols produced by the linker scripts. So, they are fixed-up
at run-time if ENABLE_PIE is enabled.

To make it work in a position-indepenent manner, use BL_CODE_BASE and
BL_END, both of which are relocatable.

Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

uniphier: pass SCP base address as a function parameter

Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(),
which is not handy for PIE.

Towards the goal of making this really positi

uniphier: pass SCP base address as a function parameter

Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(),
which is not handy for PIE.

Towards the goal of making this really position-independent, pass in
image_info->image_base.

Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

uniphier: set buffer offset and length for io_block dynamically

Currently, the .buffer field in io_block_dev_spec is statically set,
which is not handy for PIE.

Towards the goal of making this real

uniphier: set buffer offset and length for io_block dynamically

Currently, the .buffer field in io_block_dev_spec is statically set,
which is not handy for PIE.

Towards the goal of making this really position-independent, set the
buffer length and length in the uniphier_io_block_setup() function.

Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

uniphier: use more mmap_add_dynamic_region() for loading images

Currently, uniphier_bl2_mmap hard-codes the memory region needed for
loading other images.

Towards the goal of making this really pos

uniphier: use more mmap_add_dynamic_region() for loading images

Currently, uniphier_bl2_mmap hard-codes the memory region needed for
loading other images.

Towards the goal of making this really position-independent, call
mmap_add_dynamic_region() before that region gets accessed.

Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

bl_common: add BL_END macro

Currently, the end address macros are defined per BL, like BL2_END,
BL31_END, BL32_END. They are not handy in the common code shared
between multiple BL stages.

This com

bl_common: add BL_END macro

Currently, the end address macros are defined per BL, like BL2_END,
BL31_END, BL32_END. They are not handy in the common code shared
between multiple BL stages.

This commit introduces BL_END, which is equivalent to BL{2,31,32}_END,
and will be useful for the BL-common code.

Change-Id: I3c39bf6096d99ce920a5b9fa21c0f65456fbfe8a
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...