plat/arm: allow boards to specify second DRAM Base address

The base address for second DRAM varies across different platforms.
So allow platforms to define second DRAM by moving Juno/SGM-775 specifi

plat/arm: allow boards to specify second DRAM Base address

The base address for second DRAM varies across different platforms.
So allow platforms to define second DRAM by moving Juno/SGM-775 specific
definition of second DRAM base address to Juno/SGM-775 board definition
respectively, SGI/RD specific definition of DRAM 2 base address to SGI
board definition.

Change-Id: I0ecd3a2bd600b6c7019c7f06f8c452952bd07cae
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS

A TZC400 can have upto 4 filters and the number of filters instantiated
within a TZC400 is platform dependent. So allow platforms to define the

plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS

A TZC400 can have upto 4 filters and the number of filters instantiated
within a TZC400 is platform dependent. So allow platforms to define the
value of PLAT_ARM_TZC_FILTERS by moving the existing Juno specific
definition of PLAT_ARM_TZC_FILTERS to Juno board definitions.

Change-Id: I67a63d7336595bbfdce3163f9a9473e15e266f40
Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>

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Merge changes I5ca7a004,Ibcb336a2 into integration

* changes:
board/rdn1edge: use CREATE_SEQ helper macro to compare chip count
build_macros: add create sequence helper function

board/rdn1edge: use CREATE_SEQ helper macro to compare chip count

Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalabl

board/rdn1edge: use CREATE_SEQ helper macro to compare chip count

Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalable
approach to increase the valid chip count sequence in the future.

Change-Id: I5ca7a00460325c156b9e9e52b2bf656a2e43f82d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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build_macros: add create sequence helper function

Add `CREATE_SEQ` function to generate sequence of numbers starting from
1 to allow easy comparison of a user defined macro with non-zero
positive nu

build_macros: add create sequence helper function

Add `CREATE_SEQ` function to generate sequence of numbers starting from
1 to allow easy comparison of a user defined macro with non-zero
positive numbers.

Change-Id: Ibcb336a223d958154b1007d08c428fbaf1e48664
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

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corstone700: fdts: using DDR memory and XIP rootfs

This patch allows to use DDR address in memory node because on FPGA we
typically use DDR instead of shared RAM.

This patch also modifies the kerne

corstone700: fdts: using DDR memory and XIP rootfs

This patch allows to use DDR address in memory node because on FPGA we
typically use DDR instead of shared RAM.

This patch also modifies the kernel arguments to allow the rootfs to be
mounted from a direct mapping of the QSPI NOR flash using the physmap
driver in the kernel. This allows to support CRAMFS XIP.

Change-Id: I4e2bc6a1f48449c7f60e00f5f1a698df8cb2ba89
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Merge changes from topic "corstone700" into integration

* changes:
corstone700: set UART clocks to 32MHz
corstone700: clean-up as per coding style guide
Corstone700: add support for mhuv2 in a

Merge changes from topic "corstone700" into integration

* changes:
corstone700: set UART clocks to 32MHz
corstone700: clean-up as per coding style guide
Corstone700: add support for mhuv2 in arm TF-A

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Merge "coverity: fix MISRA violations" into integration

Merge "FVP: Fix BL31 load address and image size for RESET_TO_BL31=1" into integration

coverity: fix MISRA violations

Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
underscore, shall not be d

coverity: fix MISRA violations

Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c

Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

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Merge changes I4e95678f,Ia7c28704,I1bb04bb4,I93d96dca,I50aef5dd into integration

* changes:
Fix boot failures on some builds linked with ld.lld.
trusty: generic-arm64-smcall: Support gicr addres

Merge changes I4e95678f,Ia7c28704,I1bb04bb4,I93d96dca,I50aef5dd into integration

* changes:
Fix boot failures on some builds linked with ld.lld.
trusty: generic-arm64-smcall: Support gicr address
trusty: Allow gic base to be specified with GICD_BASE
trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE
Fix clang build if CC is not in the path.

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Add Matterhorn CPU lib

Also update copyright statements

Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Add CPULib for Klein Core

Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

FVP: Fix BL31 load address and image size for RESET_TO_BL31=1

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except

FVP: Fix BL31 load address and image size for RESET_TO_BL31=1

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.

Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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TBBR: Reduce size of hash buffers when possible

The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-3

TBBR: Reduce size of hash buffers when possible

The TBBR implementation extracts hashes from certificates and stores
them in static buffers. TF-A supports 3 variants of SHA right now:
SHA-256, SHA-384 and SHA-512. When support for SHA-512 was added in
commit 9a3088a5f509084e60d9c55bf53985c5ec4ca821 ("tbbr: Add build flag
HASH_ALG to let the user to select the SHA"), the hash buffers got
unconditionally increased from 51 to 83 bytes each. We can reduce that
space if we're using SHA-256 or SHA-384.

This saves some BSS space in both BL1 and BL2:
- BL1 with SHA-256: saving 168 bytes.
- BL1 with SHA-384: saving 80 bytes.
- BL2 with SHA-256: saving 384 bytes.
- BL2 with SHA-384: saving 192 bytes.

Change-Id: I0d02e5dc5f0162e82339c768609c9766cfe7e2bd
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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TBBR: Reduce size of ECDSA key buffers

The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each a

TBBR: Reduce size of ECDSA key buffers

The TBBR implementation extracts public keys from certificates and
stores them in static buffers. DER-encoded ECDSA keys are only 91 bytes
each but were each allocated 294 bytes instead. Reducing the size of
these buffers saves 609 bytes of BSS in BL2 (294 - 91 = 203 bytes for
each of the 3 key buffers in use).

Also add a comment claryfing that key buffers are tailored on RSA key
sizes when both ECDSA and RSA keys are used.

Change-Id: Iad332856e7af1f9814418d012fba3e1e9399f72a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banav

corstone700: set UART clocks to 32MHz

Adding support for 32MHz UART clock and selecting it as the
default UART clock

Change-Id: I9541eaff70424e85a3b5ee4820ca0e7efb040d2c
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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corstone700: clean-up as per coding style guide

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: Avinash Mehta <

corstone700: clean-up as per coding style guide

Running checkpatch.pl on the codebase and making required changes

Change-Id: I7d3f8764cef632ab2a6d3c355c68f590440b85b8
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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Corstone700: add support for mhuv2 in arm TF-A

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main cha

Corstone700: add support for mhuv2 in arm TF-A

Note: This patch implements in-band messaging protocol only.
ARM has launched a next version of MHU i.e. MHUv2 with its latest
subsystems. The main change is that the MHUv2 is now a distributed IP
with different peripheral views (registers) for the sender and receiver.

Another main difference is that MHUv1 duplex channels are now split into
simplex/half duplex in MHUv2. MHUv2 has a configurable number of
communication channels. There is a capability register (MSG_NO_CAP) to
find out how many channels are available in a system.

The register offsets have also changed for STAT, SET & CLEAR registers
from 0x0, 0x8 & 0x10 in MHUv1 to 0x0, 0xC & 0x8 in MHUv2 respectively.

0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | | SET | | |
------------------------....-----
Transmit Channel

0x0 0x4 0x8 0xC 0x1F
------------------------....-----
| STAT | | CLR | | | |
------------------------....-----
Receive Channel

The MHU controller can request the receiver to wake-up and once the
request is removed, the receiver may go back to sleep, but the MHU
itself does not actively put a receiver to sleep.

So, in order to wake-up the receiver when the sender wants to send data,
the sender has to set ACCESS_REQUEST register first in order to wake-up
receiver, state of which can be detected using ACCESS_READY register.
ACCESS_REQUEST has an offset of 0xF88 & ACCESS_READY has an offset
of 0xF8C and are accessible only on any sender channel.

This patch adds necessary changes in a new file required to support the
latest MHUv2 controller. This patch also needs an update in DT binding
for ARM MHUv2 as we need a second register base (tx base) which would
be used as the send channel base.

Change-Id: I1455e08b3d88671a191c558790c503eabe07a8e6
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>

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rockchip: fix definition of struct param_ddr_usage

In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage n

rockchip: fix definition of struct param_ddr_usage

In extreme cases, the number of secure regions is one more than
non-secure regions. So array "s_base" and "s_top"s size
in struct param_ddr_usage need to be adjust to "DDR_REGION_NR_MAX + 1".

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: Ifc09da2c8f8afa1aebcc78f8fbc21ac95abdece2

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rcar_gen3: plat: Minor coding style fix for rcar_version.h

Use space after #define consistently, drop useless parenthesis,
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmai

rcar_gen3: plat: Minor coding style fix for rcar_version.h

Use space after #define consistently, drop useless parenthesis,
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I72846d8672cab09b128e3118f4b7042a5a9c0df5

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rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream updat

rcar_gen3: plat: Update IPL and Secure Monitor Rev.2.0.6

Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I70c3d873b1d05075257034aee5e19c754be911e0

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rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.40.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.40.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: If675796a2314e769602af21bf5cc6b10962d4f29

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rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.39.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut

rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N

[IPL/DDR]
- Update H3, M3, M3N DDR setting rev.0.39.

Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: I0dbf8091f9de9bb6d2d4f94007a5813fff14789f

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rcar_gen3: drivers: board: Add new board revision for M3ULCB

Board Revision[2:0]
3'b000 Rev1.0
3'b011 Rev3.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Marek Vas

rcar_gen3: drivers: board: Add new board revision for M3ULCB

Board Revision[2:0]
3'b000 Rev1.0
3'b011 Rev3.0 [New]

Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update
Change-Id: Ie4f3ac83cc20120ede21052f7452327049565e60

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