Merge changes I8bdf79e8,I0eebfdf6 into integration

* changes:
feat(mt8189): add reset and poweroff function for PSCI call
feat(mt8189): link prebuilt library

Merge "docs(security): security advisory for CVE-2024-5660" into integration

refactor(build): pass TF_CFLAGS to the assembler

The assembler is already invoked through the gcc/llvm wrapper so will
understand the TF_CFLAGS out of the box. TF_CFLAGS are also quite
comprehensive

refactor(build): pass TF_CFLAGS to the assembler

The assembler is already invoked through the gcc/llvm wrapper so will
understand the TF_CFLAGS out of the box. TF_CFLAGS are also quite
comprehensive. So don't duplicate the definitions and use it directly.
This also allows to absorb TF_CFLAGS_$(ARCH) and CPPFLAGS and reduce
the number of permutations of flags we pass.

Change-Id: I801cea0421dab5a07bf720be9693dce3ef220dcf
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): absorb CFLAGS into TF_CFLAGS

CFLAGS is the standard and expected variable for passing flags to the
compiler. The build system also uses TF_CFLAGS to define its own flags.
But the bu

refactor(build): absorb CFLAGS into TF_CFLAGS

CFLAGS is the standard and expected variable for passing flags to the
compiler. The build system also uses TF_CFLAGS to define its own flags.
But the build rules need to specify both. So append CFLAGS to TF_CFLAGS
so that only the latter needs to be passed.

Change-Id: I4abb6c9dfc252a805063691e8a100f0ec0c785ad
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not

refactor(build): use a standard rule to run the preprocessor

There are a few, functionally identical, ways to call the preprocessor
on a non-C file, depending on the file. They differ in subtle, not
entirely correct, ways - one is missing a dependency to the makefiles,
another generates its .d inline, and the prints are different. That has
resulted in platforms reimplementing this functionality, making the
build brittle - a change to the overall build system doesn't propagate.
So add a MAKE_PRE macro that will make a rule with all the bells and
whistles to run the preprocessor on an arbitrary file.

This patch converts the arm platforms' cot_descriptors DTS rules. The
files are renamed to fit with the build rule and all extra flags are
dropped. Those flags are only necessary for building BL2 c files, which
will be passed to the output C file. Only the DTS flags are needed for
the preprocessing step, which will be passed automatically.

Change-Id: I3c1cc0ecf93b87d828f868214928c1bc9bcb5758
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): place all cflags setting in one place

The top-level Makefile has to come up with a list of flags to pass to
the compiler. It has to do so while considering a variety of options and

refactor(build): place all cflags setting in one place

The top-level Makefile has to come up with a list of flags to pass to
the compiler. It has to do so while considering a variety of options and
constraints. This has generally done in the most convenient place in the
file. However, it causes problems with evaluation - options may be set
after they are used, there may be platform dependencies, DEFINES, etc.
As a result flags must be lazily evaluated and they lack any cohesive
design.

To enable a solution to this, extract all CFLAGS/LDFLAGS/ASFLAGS
configuration to a new file. Reorder rules slightly to put related rules
closer together and call the entire thing as late as possible - after
platform.mk and after the DEFINES are known.

There is a small number of libraries that set flags in their own sub
makefiles. As these contain the entire feature, do not move their flags
to keep them self-contained. This is okay as these makefile will be
evaluated before the cflags.

Change-Id: I1b6f69adbf885396632949966b77a5710d1c851d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(build): simplify ENABLE_LTO checking

We do not support LTO with AArch32. The standard way to enforce this is
by having a rule to fail the build when this happens. There are no
AArch32 platf

refactor(build): simplify ENABLE_LTO checking

We do not support LTO with AArch32. The standard way to enforce this is
by having a rule to fail the build when this happens. There are no
AArch32 platforms which (incorrectly) try to enable LTO, so add this
rule. The benefit is that we no longer have to check the ENABLE_LTO with
ARCH whenever it is used.

Change-Id: Ic4086a1f5122269bda1d75bd4474b98fde35b5af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpus): workaround for Cortex-X3 erratum 3213672

Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.

This erratum can be worked around by se

fix(cpus): workaround for Cortex-X3 erratum 3213672

Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.

This erratum can be worked around by setting CPUACTLR_EL1[36]
before enabling icache.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40

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fix(cpus): workaround for Cortex-X3 erratum 3827463

Cortex-X3 erratum 3827463 is a Cat B erratum that applies to
r0p0, r1p0 and r1p1. It is fixed in r1p2.

This erratum can be avoided by setting CPU

fix(cpus): workaround for Cortex-X3 erratum 3827463

Cortex-X3 erratum 3827463 is a Cat B erratum that applies to
r0p0, r1p0 and r1p1. It is fixed in r1p2.

This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1d4a2b9641400d8b9061f7cb32a8312c3995613e

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fix(cpus): workaround for Cortex-X3 erratum 3692984

Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.

The erratum can be avoided by disabling

fix(cpus): workaround for Cortex-X3 erratum 3692984

Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.

The erratum can be avoided by disabling the
affected prefetcher setting CPUACTLR6_EL1[41].

SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I054b47d33fd1ff7bde3ae12e8ee3d99e9203965f

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feat(mt8189): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I8bdf79e81f2fa1920d02af904d53eb610825d5e2
Signed-off-by: Gavin Liu <gavin.liu@m

feat(mt8189): add reset and poweroff function for PSCI call

Add reset and poweroff function for PSCI call.

Change-Id: I8bdf79e81f2fa1920d02af904d53eb610825d5e2
Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>

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feat(mt8189): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided
by MTKLIB_PATH. Otherwise, it will use stub implementation.

Signed-off-by: Gavin Liu <gavin.l

feat(mt8189): link prebuilt library

If MTKLIB_PATH is provided, the build will use the library provided
by MTKLIB_PATH. Otherwise, it will use stub implementation.

Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
Change-Id: I0eebfdf69ab1d4f7788b3cc6de26e47587f6b906

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fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or f

fix(el3-spmc): fixed x8-x17 register handling for FFA 1.2

Changed spmd_smc_switch_state to return all 18 registers for 64 bit
calls, and set x8-17 to zero if necessary.

BREAKING CHANGE: Zeroes or forwards a different set of registers,
depending on the FF-A version of the source and destination.
E.g. a call from a v1.1 caller to a v1.2 destination will zero
out the extended registers, which is different from the old behavior
of forwarding everything to EL2 SPMC, but only x0-x7 to the EL3 SPMC.

Change-Id: Ic31755af0fbb117b0ed74565fba9decebab353c4
Signed-off-by: Jay Monkman <jmonkman@google.com>
Signed-off-by: Andrei Homescu <ahomescu@google.com>

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docs(security): security advisory for CVE-2024-5660

Add CVE-2024-5660 security advisory document.

Change-Id: I0d0428061f60b6fe83d03362b27b960f6ddcc6f4
Signed-off-by: Govindraj Raja <govindraj.raja@

docs(security): security advisory for CVE-2024-5660

Add CVE-2024-5660 security advisory document.

Change-Id: I0d0428061f60b6fe83d03362b27b960f6ddcc6f4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "feat(st): use and override default MBedTLS config" into integration

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width o

fix(console): ensured proper bitwise shift operation

This corrects the MISRA violation C2012-12.2:
Used BIT_32() rather than manual bit shifting to prevent shifting
beyond the essential type width of the left operand. This ensures
compliance with MISRA C 2012 Rule 12.2.

Change-Id: I1a4ed9366bd9ab773c4a5f6798508ead991593d2
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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fix(xilinx): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(xilinx): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I1640a5f40f9471abf4023234ebdbc47018473c56
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "feat(smccc): introduce TPM Start SMC" into integration

Merge "feat(cpufeat): add support for FEAT_FGWTE3" into integration

Merge "fix(qti): allow secure r/w to the EUD enable register" into integration

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MP

feat(cpufeat): add support for FEAT_FGWTE3

Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.

Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)

TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)

Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3

Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge changes from topic "xlnx_fix_gen_op_datatype" into integration

* changes:
fix(el3-runtime): typecast operands to match data type
fix(arm): typecast operands to match data type

Merge "fix(tpm): extend timeout before reading data" into integration

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SP

feat(smccc): introduce TPM Start SMC

To support TPM start method compatible with pre-FFA configuration (to
support SPM_MM) introduce an SMC FID el3 vendor specific range. This
SMC is forwarded to SPM_MM module which converts into a MM_COMMUNICATE
to interact with Secure partition.

TPM Start method is mentioned in TCG ACPI spec section 3.3.1
https://trustedcomputinggroup.org/wp-content/uploads/TCG-ACPI-Specification-Version-1.4-Revision-15_pub.pdf

As this patch introduces a new sub service, increment minor version
of Vendor EL3 service.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I61698018e6bc33c9b389ac905fe158810af21bfa

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feat(st): use and override default MBedTLS config

Each time MbedTLS is updated, the default config may be updated. As
STM32MP platforms have their own config file, this needs to be aligned.
To avoid

feat(st): use and override default MBedTLS config

Each time MbedTLS is updated, the default config may be updated. As
STM32MP platforms have their own config file, this needs to be aligned.
To avoid this alignment, directly include the default config and
override some values for ST platforms, mainly heap size.
MBEDTLS_MPI_WINDOW_SIZE is also kept to avoid behavior change.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6a9c3141451ab7b11906a7139549d31cfff0581a

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