feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device an

feat(stm32mp2): add some platform helpers

Update STM32MP2 the platform files.
Implement the helpers for STM32MP2, as we have them for STM32MP1:
stm32mp_is_single_core, stm32mp_check_closed_device and
stm32mp_is_auth_supported

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I1554efdb05338f07b292e77175db5a564cc25c78

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feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(t

feat(st-drivers): add RISAF driver

Introduction of Resource Isolation Slave for Address space - Full
(RISAF) driver to configure main memory regions with access rights
defined in device node in DT(through FCONF compliance) or statically.

The driver is enabled as BL2 sources. Add driver-related platform
services.
RISAF base addresses and key size are set in platform definitions.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Iae99985e8db7cb2b27f9ca25669e74c8e08792d2

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Merge "fix(st-crypto): resolve MISRA warning in HASH" into integration

Merge changes I801cea04,I4abb6c9d,I3c1cc0ec,I1b6f69ad,Ic4086a1f into integration

* changes:
refactor(build): pass TF_CFLAGS to the assembler
refactor(build): absorb CFLAGS into TF_CFLAGS
refac

Merge changes I801cea04,I4abb6c9d,I3c1cc0ec,I1b6f69ad,Ic4086a1f into integration

* changes:
refactor(build): pass TF_CFLAGS to the assembler
refactor(build): absorb CFLAGS into TF_CFLAGS
refactor(build): use a standard rule to run the preprocessor
refactor(build): place all cflags setting in one place
refactor(build): simplify ENABLE_LTO checking

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feat(fdts): add RISAF nodes for STM32MP25

Add RISAF2 and RISAF4 nodes in STM32MP25 SoC DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.ba

feat(fdts): add RISAF nodes for STM32MP25

Add RISAF2 and RISAF4 nodes in STM32MP25 SoC DT file.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I96f96267292e7f7a498a87c60e35310e25b41d6d

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feat(stm32mp2-fdts): add memory firewall node

add RIF memory firewall node for STM32MP257F-DK board.

Change-Id: I1b6b094a3f6209f996a2ff5d590f081a68d9c7a9
Signed-off-by: Maxime Méré <maxime.mere@fos

feat(stm32mp2-fdts): add memory firewall node

add RIF memory firewall node for STM32MP257F-DK board.

Change-Id: I1b6b094a3f6209f996a2ff5d590f081a68d9c7a9
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2-fdts): add firewall nodes in fw-config

The stm32mp257f-ev board fw-config DT file now includes a dtsi file that
describes the DDR firewall configuration.

Signed-off-by: Yann Gautier <

feat(stm32mp2-fdts): add firewall nodes in fw-config

The stm32mp257f-ev board fw-config DT file now includes a dtsi file that
describes the DDR firewall configuration.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I3300b00ba6e59b8df4f02db531edd590683c333f

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feat(stm32mp2): add RIF dt-binding defines

Add defines for RIF sub-system configuration (RIFSC, RISAB, RISAF,
RISUP and RIMU). List RIFSC identifiers in a platform-specific file.

Signed-off-by: Nic

feat(stm32mp2): add RIF dt-binding defines

Add defines for RIF sub-system configuration (RIFSC, RISAB, RISAF,
RISUP and RIMU). List RIFSC identifiers in a platform-specific file.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Loic Pallardy <loic.pallardy@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I770fb7d1866caf899171c80cb6ce65735ac97fc9

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feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board

Add an st-mem-encrypt node in a dedicated file. This file will be
included by boards fw-config file if they support encryption.

Change-Id

feat(stm32mp1-fdts): add MCE support for STM32MP13 DK board

Add an st-mem-encrypt node in a dedicated file. This file will be
included by boards fw-config file if they support encryption.

Change-Id: I7d2b278da144a10c10d194d0475ab11b1bc142bb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly gene

feat(stm32mp1): prepare DDR secure area encryption for STM32MP13

The Memory Cipher Engine (MCE) defines the DDR secure area with
specific security setup (encryption).
Its master key is randomly generated (using RNG driver).
Initialize and configure MCE IP on platform side only if
authentication is supported at SoC level.

Change-Id: I034f45b0fd547d924cbc92c42298e1f3b1e7343c
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by

feat(stm32mp1): enable MCE driver for STM32MP13

Enabled as BL2 sources.
Add MCE base address and key size in platform definitions.

Change-Id: Icb7d9d7a56806a86e6d0a76640a375a5b5e88a2a
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region

feat(st-drivers): add Memory Cipher Engine driver

Memory Cipher Engine (MCE) defines, in a given address space, one region
with specific security setup (encryption).
FCONF compliance ensures region definition through DT.

Change-Id: I1bca9c0a89af88a72651e1a71e3f8950807eec40
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(dt-bindings): add MCE DT bindings for STM32MP13

This makes the region definition easier in DT, with explicit parameters.

Change-Id: I4e3f6e6d31288ccec807f3fc71544d8cf39ef1e5
Signed-off-by: Nic

feat(dt-bindings): add MCE DT bindings for STM32MP13

This makes the region definition easier in DT, with explicit parameters.

Change-Id: I4e3f6e6d31288ccec807f3fc71544d8cf39ef1e5
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

S

fix(st-crypto): resolve MISRA warning in HASH

Resolve folowing MISRA warning in stm32_hash :
MISRA-c2012-10.3 MISRA-c2012-10.4 MISRA-c2012-17.7 MISRA-c2012-17.8
MISRA-c2012-18.4 MISRA-c2012-21.15

Signed-off-by: Thomas BOURGOIN <thomas.bourgoin@foss.st.com>
Change-Id: Ia37b5b0f706701ca2827d47c9360dfcf83a48fc0

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fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve

fix(st-crypto): improve RNG health test configuration

The default health test configuration in RNG_HTCR is not good enough.
It implies too many zero random generations.
Set a better value to improve the IP behavior.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I7e05e52466be68fdbf5439931a9f01dcfa57a24d

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feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608

feat(st): add RNG minor version

Some specific configurations (NIST/HTCR) can depend on the RNG IP minor
version used.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I3608bd5cad77616bf0c031c66a8312b65d3e68c5

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feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instanc

feat(st-crypto): add multi instance and error management in RNG driver

Allows the driver to initialize as many RNG instances as enabled in the
device tree. The driver will still use only one instance for the TF-A
purpose as it needs only one to work. The others are activated because
needed by specific IPs.

Seed errors are now also checked after null data read. The Reference
Manual recommends to always verify that RNG_DR is different from zero.
Because when it is the case a seed error can occur between RNG_SR
polling and RND_DR output reading (rare event).

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Ie4d7f01f4ffe5a9e2d0e5e7317b008edd3b80a17

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feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892

feat(stm32mp2): add HASH and RNG compilation

Add the drivers compilation in STM32MP2 platform.mk.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9916d1c3da3f9f68ea4d52ca15ea7892eff66c99

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feat(stm32mp25-fdts): add RNG node

IP aligned with STM32MP13, use same compatible.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Cha

feat(stm32mp25-fdts): add RNG node

IP aligned with STM32MP13, use same compatible.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I230c405a8e2baaf952d90646aaa54239fed9fdf4

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fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(dcc): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Iba1627367d9bb8c2f5e4a9d45de96dd891356abc
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signe

feat(gic): make IRQ groups optional

There are systems which define no Group 0 interrupts, make both
G0 and G1S groups optional to make it possible for those systems
to use the generic driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I39e366ed1988847bfa288adc0732d9b864e58bbd

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Merge "fix(console): add missing curly braces" into integration

fix(console): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement. Enclosed statement bod

fix(console): add missing curly braces

This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement. Enclosed statement body within the curly
braces.

Change-Id: I3fffc660cae07ae386d36bad46ae1d528a17b630
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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Merge "fix(console): ensured proper bitwise shift operation" into integration

Merge changes from topic "ar/x3_errata" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 3213672
fix(cpus): workaround for Cortex-X3 erratum 3827463
fix(cpus): workaroun

Merge changes from topic "ar/x3_errata" into integration

* changes:
fix(cpus): workaround for Cortex-X3 erratum 3213672
fix(cpus): workaround for Cortex-X3 erratum 3827463
fix(cpus): workaround for Cortex-X3 erratum 3692984

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