Merge "plat/arm/fvp: Support performing SDEI platform setup in runtime" into integration

plat/arm/fvp: Support performing SDEI platform setup in runtime

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead

plat/arm/fvp: Support performing SDEI platform setup in runtime

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.

Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "Tegra: introduce support for SMCCC_ARCH_SOC_ID" into integration

Merge "Implement workaround for AT speculative behaviour" into integration

Implement workaround for AT speculative behaviour

During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instru

Implement workaround for AT speculative behaviour

During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instruction using out-of-context
translation regime.

Workaround is implemented as below during EL's (EL1 or EL2)
"context_restore" operation:
1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1
bits for EL1 or EL2 (stage1 and stage2 disabled)
2. Save all system registers except TCR and SCTLR (for EL1 and EL2)
3. Do memory barrier operation (isb) to ensure all
system register writes are done.
4. Restore TCR and SCTLR registers (for EL1 and EL2)

Errata details are available for various CPUs as below:
Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923
Cortex-A53: 1530924

More details can be found in mail-chain:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html

Currently, Workaround is implemented as build option which is default
disabled.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0

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Merge changes I35c5abd9,I99e64245 into integration

* changes:
SPMD: extract SPMC DTB header size from SPMD
SPMD: code/comments cleanup

Merge "doc: Reorganize maintainers.rst file" into integration

Merge "doc: Update various process documents" into integration

doc: Reorganize maintainers.rst file

The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is somet

doc: Reorganize maintainers.rst file

The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is sometimes hard to find the information.

Introduce categories (core code, drivers/libraries/framework, ...) and
classify each module in the right one.

Note that the core code category is pretty much empty right now but the
plan would be to expand it with further modules (e.g. PSCI, SDEI, TBBR,
...) in a future patch.

Change-Id: Id68a2dd79a8f6b68af5364bbf1c59b20c05f8fe7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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doc: Update various process documents

Most of the changes consist in using the new code owners terminology
(from [1]).

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-

doc: Update various process documents

Most of the changes consist in using the new code owners terminology
(from [1]).

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Change-Id: Icead20e9335af12aa47d3f1ac5d04ca157b20c82
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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SPMD: extract SPMC DTB header size from SPMD

Currently BL2 passes TOS_FW_CONFIG address and size through registers to
BL31. This corresponds to SPMC manifest load address and size. The SPMC
manifest

SPMD: extract SPMC DTB header size from SPMD

Currently BL2 passes TOS_FW_CONFIG address and size through registers to
BL31. This corresponds to SPMC manifest load address and size. The SPMC
manifest is mapped in BL31 by dynamic mapping. This patch removes BL2
changes from generic code (which were enclosed by SPD=spmd) and retrieves
SPMC manifest size directly from within SPMD. The SPMC manifest load
address is still passed through a register by generic code.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f

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SPMD: code/comments cleanup

As a follow-up to bdd2596d4, and related to SPM Dispatcher
EL3 component and SPM Core S-EL2/S-EL1 component: update
with cosmetic and coding rules changes. In addition:
-

SPMD: code/comments cleanup

As a follow-up to bdd2596d4, and related to SPM Dispatcher
EL3 component and SPM Core S-EL2/S-EL1 component: update
with cosmetic and coding rules changes. In addition:
-Add Armv8.4-SecEL2 arch detection helper.
-Add an SPMC context (on current core) get helper.
-Return more meaningful error return codes.
-Remove complexity in few spmd_smc_handler switch-cases.
-Remove unused defines and structures from spmd_private.h

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe

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Tegra: introduce support for SMCCC_ARCH_SOC_ID

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC

Tegra: introduce support for SMCCC_ARCH_SOC_ID

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC_ARCH_SOC_ID test.

<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
TEST COMPLETE Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44

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drivers: stm32mp1 clocks: fix debug trace on clock enable/disable

Adds missing terminal new line character '\n' to debug traces,
fix format as index is an unsigned value and use present tense rather

drivers: stm32mp1 clocks: fix debug trace on clock enable/disable

Adds missing terminal new line character '\n' to debug traces,
fix format as index is an unsigned value and use present tense rather
than past tense in the printed message.

Change-Id: I88c06ef4d3a11d97ff8e96875a3dd0f58a3c98b6
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32mp1 clocks: enable system clocks during initialization

Enable few system clocks at related BL initialization.

Change-Id: I12b35e8cdc128b993de4a1dc4c6e9d52624dd8d9
Signed-off-by: Etien

drivers: stm32mp1 clocks: enable system clocks during initialization

Enable few system clocks at related BL initialization.

Change-Id: I12b35e8cdc128b993de4a1dc4c6e9d52624dd8d9
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32mp1 clocks: prevent crash on always on clocks

Oscillators and PLLs are not gated on stm32mp_clk_enable/disable()
calls. This change prevents functions to panic when called for such
alw

drivers: stm32mp1 clocks: prevent crash on always on clocks

Oscillators and PLLs are not gated on stm32mp_clk_enable/disable()
calls. This change prevents functions to panic when called for such
always-on clocks. Gating these clocks is out of the scope of
this change.

Change-Id: Ie730553dea480b529de942446176db9119587832
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32mp1 clocks: add RTC as a gateable clock

Adds RTC clock to the list of the supported clocks. This allows
stm32mp_clk_*() API functions to enable, disable and set and get
rate for the cl

drivers: stm32mp1 clocks: add RTC as a gateable clock

Adds RTC clock to the list of the supported clocks. This allows
stm32mp_clk_*() API functions to enable, disable and set and get
rate for the clock RTC clock.

Change-Id: I8efc3f00b1f22d1912f59d1846994e9e646d6614
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32mp1 clocks: support shifted clock selector bit masks

The current implementation optimizes memory consumed by gateable
clock table by storing bit mask and bit shift with 1 byte each.
Th

drivers: stm32mp1 clocks: support shifted clock selector bit masks

The current implementation optimizes memory consumed by gateable
clock table by storing bit mask and bit shift with 1 byte each.
The issue is that register selector bit masks above the 7th LSBit
cannot be stored.

This change uses the shift info to shift the mask before it is used,
allowing clock selector register bit fields to be spread on the 32 bits
of the register as long as the mask fits in 8 contiguous bit at most.

This change is needed to add the RTC clock to the gateable clocks table.

Change-Id: I8a0fbcbf20ea383fb3d712f5064d2d307e44465d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32mp1 clocks: allow tree lookup for several system clocks

Oscillators, PLLs and some system clocks can be related straight to
a parent clock. Prior this change were only oscillators and

drivers: stm32mp1 clocks: allow tree lookup for several system clocks

Oscillators, PLLs and some system clocks can be related straight to
a parent clock. Prior this change were only oscillators and few
clocks supported by this look up. This changes adds PLLs and other
system clocks. This enables for flexible use of clock tree exploration
when computing a clock frequency value.

Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat/stm32mp1: fdt helpers for secure aware gpio bank

New helper functions to get GPIO banks configuration from the FDT.

stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to
differentiate

plat/stm32mp1: fdt helpers for secure aware gpio bank

New helper functions to get GPIO banks configuration from the FDT.

stm32_get_gpio_bank_pinctrl_node() allows stm32mp platforms to
differentiate specific GPIO banks when these are defined with a specific
path in the FDT.

fdt_get_gpio_bank_pin_count() returns the number of pins in a GPIO bank
as it depends on the SoC variant.

Change-Id: I4481774152b3c6bf35bf986f58e357c2f9c19176
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat/st: move GPIO bank helper function to platform source files

Relation between GPIO banks and their base address and offset address
if platform dependent. This change moves helper functions
stm32

plat/st: move GPIO bank helper function to platform source files

Relation between GPIO banks and their base address and offset address
if platform dependent. This change moves helper functions
stm32_get_gpio_bank_base() and stm32_get_gpio_bank_offset() from
plat/st/common to plat/st/stm32mp1/.

Change-Id: Id3d03e585746aa5509c6fab7d88183a92d561e3f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge "Fix SMCCC_ARCH_SOC_ID implementation" into integration

Merge changes from topic "fdt_wrappers_rework" into integration

* changes:
arm_fpga: Read UART address from DT
arm_fpga: Read GICD and GICR base addresses from DT
arm_fpga: Read generic timer

Merge changes from topic "fdt_wrappers_rework" into integration

* changes:
arm_fpga: Read UART address from DT
arm_fpga: Read GICD and GICR base addresses from DT
arm_fpga: Read generic timer counter frequency from DT
arm_fpga: Use Generic UART

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Merge changes from topic "fdt_wrappers_rework" into integration

* changes:
plat/stm32: Use generic fdt_get_stdout_node_offset()
fdt/wrappers: Introduce code to find UART DT node
plat/stm32: Us

Merge changes from topic "fdt_wrappers_rework" into integration

* changes:
plat/stm32: Use generic fdt_get_stdout_node_offset()
fdt/wrappers: Introduce code to find UART DT node
plat/stm32: Use generic fdt_get_reg_props_by_name()

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Tegra194: validate C6 power state type

This patch validates that PSTATE_STANDBY is set as the C6 power state type.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846

Tegra194: validate C6 power state type

This patch validates that PSTATE_STANDBY is set as the C6 power state type.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846ab61c007eeba3c180e5aa

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