make, doc: Add build option to create chain of trust at runtime

Added a build option 'COT_DESC_IN_DTB' to create chain of trust
at runtime using fconf.

Signed-off-by: Manish V Badarkhe <Manish.Bada

make, doc: Add build option to create chain of trust at runtime

Added a build option 'COT_DESC_IN_DTB' to create chain of trust
at runtime using fconf.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I92b257ac4ece8bbf56f05a41d1e4056e2422ab89

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Merge "doc: Update CoT binding to make it more generic" into integration

doc: Update CoT binding to make it more generic

Updated the CoT binding document to show chain of trust relationship
with the help of 'authentication method' and 'authentication data'
instead of sho

doc: Update CoT binding to make it more generic

Updated the CoT binding document to show chain of trust relationship
with the help of 'authentication method' and 'authentication data'
instead of showing content of certificate and fixed rendering issue
while creating html page using this document.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib48279cfe786d149ab69ddc711caa381a50f9e2b

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drivers/stm32_hash: register resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared

drivers/stm32_hash: register resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared peripheral because BL2 does not embed the shared resources
driver.

Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32_gpio: register GPIO resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf8

drivers/stm32_gpio: register GPIO resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf887605
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32_iwdg: register IWDG resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd

drivers/stm32_iwdg: register IWDG resources as secure or not

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers/stm32mp_pmic: register PMIC resources as secure or not

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f4

drivers/stm32mp_pmic: register PMIC resources as secure or not

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f434
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: register shared resource per GPIO bank/pin

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or

stm32mp1: register shared resource per GPIO bank/pin

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or non-secure.

These functions are stubbed when shared resource driver is not
embedded in the BL image so that drivers do not bother whether they
shall register or not their resources.

Change-Id: I1fe98576c072ae31f75427c9ac5c9f6c4f1b6ed1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resour

stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resource as secure or non-secure based on its SoC
interface registers base address.

These functions are stubbed when shared resources driver is not
embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded
in other BL stages do not bother whether they shall register or
not their resources.

Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: allow non-secure access to reset upon periph registration

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering s

stm32mp1: allow non-secure access to reset upon periph registration

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering state locks further registration of
peripherals.

Change-Id: I5f38f2a3481780b9a71939d95984c4821c537aa4
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: allow non-secure access to clocks upon periph registration

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering

stm32mp1: allow non-secure access to clocks upon periph registration

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering state locks further registration of peripherals.

Change-Id: If68f6d4a52c4742ba66244c6ea2d9afa08404137
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: peripheral registering

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resourc

stm32mp1: shared resources: peripheral registering

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resource assigned to respectively secure
or non-secure world.

Some resources are related to clock resources. When a resource is
registered as secure, ensure its clock dependencies are also
registered as secure. Registering a non-secure resource does not
mandate its clock dependencies are also registered as non-secure.

Change-Id: I74975be8976b8d3bf18dcc807541a072803af6e3
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: st: clock: register parent of secure clocks

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent c

drivers: st: clock: register parent of secure clocks

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent clocks of a clock registered as secure.

Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: add trace messages

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendl

stm32mp1: shared resources: add trace messages

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendly peripheral registering functions.

Change-Id: I9e207b8ce1d1e9250e242ca7e15461b9a1532f40
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge "Upgrade libfdt source files" into integration

Merge "drivers: arm: gicv3: auto-detect presence of GIC600-AE" into integration

drivers: arm: gicv3: auto-detect presence of GIC600-AE

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC6

drivers: arm: gicv3: auto-detect presence of GIC600-AE

This patch adds the IIDR value for GIC600-AE to the gicv3_is_gic600()
helper function. This helps platforms supporting this version of the
GIC600 interrupt controller to function with the generic GIC driver.

Verified with tftf-validation test suite

******************************* Summary *******************************
> Test suite 'Framework Validation'
Passed
> Test suite 'Timer framework Validation'
Passed
=================================
Tests Skipped : 0
Tests Passed : 6
Tests Failed : 0
Tests Crashed : 0
Total tests : 6
=================================
NOTICE: Exiting tests.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I518ae7b56f7f372e374e453287d76ca370fc3574

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Merge "corstone700: splitting the platform support into FVP and FPGA" into integration

corstone700: splitting the platform support into FVP and FPGA

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

fvp and fpga

- Since the FVP and F

corstone700: splitting the platform support into FVP and FPGA

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
- Enabling NEED_BL33 option
- Fixing non-secure image base: For no preloaded bl33 we want to
have the NS base set on shared ram. Setup a memory map region
for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

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fiptool: return zero status on help and help <command>

Querying the 'fiptool' for help or help <command> should return 0
return status (success) and not 1 (failure). In the other hand, if tool is
ex

fiptool: return zero status on help and help <command>

Querying the 'fiptool' for help or help <command> should return 0
return status (success) and not 1 (failure). In the other hand, if tool is
executed with any other command (not help) where command's parameters are
either missing or wrong, then the tool should return non-zero (failure). Now,
the 'usage' function caller is the one that passes the return status.

Change-Id: Id5eea91037cd810fb1e34a42e8199ef504f5daa4
Signed-off-by: Leonardo Sandoval <leonardo.sandoval@linaro.org>

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rockchip: don't crash if we get an FDT we can't parse

When we parse the param from BL2, we try to parse it as a FDT and then,
if that fails, as aux params. However, we don't sufficiently distinguish

rockchip: don't crash if we get an FDT we can't parse

When we parse the param from BL2, we try to parse it as a FDT and then,
if that fails, as aux params. However, we don't sufficiently distinguish
between failure modes in the first step: specifically, if we are given
an FDT with good magic that we can't parse for some other reason (e.g.
not enough space in our buffer), we still attempt to parse it as aux
params even though that's guaranteed to fatal. Instead, we should either
fail with a more descriptive message or continue to boot without parsing
the FDT.

This patch takes the latter approach, since all we currently get from
the FDT is non-critical UART params.

Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Change-Id: I1e98f1fcda4f78e6b45e86956288bafe58b113e4

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docs: qemu: bump to QEMU 5.0.0

Fix the version inconsistency in the same file.

I tested QEMU 5.0.0, and it worked for me.

Change-Id: I9d8ca9aae1e413410eb5676927e13ae4aee9fad8
Signed-off-by: Masahi

docs: qemu: bump to QEMU 5.0.0

Fix the version inconsistency in the same file.

I tested QEMU 5.0.0, and it worked for me.

Change-Id: I9d8ca9aae1e413410eb5676927e13ae4aee9fad8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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docs: qemu: remove unneeded root=/dev/vda2 kernel parameter

In my understanding, /dev/vda2 does not exist unless you add
virtio drive to the qemu command line.

The rootfs is already specified by '-

docs: qemu: remove unneeded root=/dev/vda2 kernel parameter

In my understanding, /dev/vda2 does not exist unless you add
virtio drive to the qemu command line.

The rootfs is already specified by '-initrd rootfs.cpio.gz'.

Change-Id: Ifdca5d4f3819d87ef7e8a08ed870872d24b86370
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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docs: qemu: add build instructions for QEMU_EFI.fd and rootfs.cpio.gz

This commit solves the limitation, "No build instructions for
QEMU_EFI.fd and rootfs-arm64.cpio.gz"

Document the steps to build

docs: qemu: add build instructions for QEMU_EFI.fd and rootfs.cpio.gz

This commit solves the limitation, "No build instructions for
QEMU_EFI.fd and rootfs-arm64.cpio.gz"

Document the steps to build them.

Change-Id: Ic6d895617cf71fe969f4aa9820dad25cc6182023
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board

Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.

It supports 1 x 288-pin DIMM, DDR4 2400M

plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board

Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.

It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC).

The iEi Puzzle-M801 board is using a custom MCU to handle board
power management. The MCU is managing the boards power LEDs, fans
and some other periferals. It's using UART for communication.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8

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