Merge "SPMC: adjust the number of EC context to max number of PEs" into integration

stm32mp1: correct crash console GPIO alternate configuration

If GPIO port for UART TX is less than 8, the register GPIO_AFRL should
be used to set the alternate. GPIO_AFRH is used if GPIO port is gr

stm32mp1: correct crash console GPIO alternate configuration

If GPIO port for UART TX is less than 8, the register GPIO_AFRL should
be used to set the alternate. GPIO_AFRH is used if GPIO port is greater
or equal to 8. The macro GPIO_TX_ALT_SHIFT is removed and the GPIO port
number is tested against GPIO_ALT_LOWER_LIMIT (=8) in
plat_crash_console_init() function.

Change-Id: Ibb62223ed6bce589bbcab59a5e986b2677e6d118
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: add plat_panic_handler function

The STM32MP1 implementation of this function will call
plat_report_exception(). It displays more information about the panic
if DEBUG is enabled.
The LR reg

stm32mp1: add plat_panic_handler function

The STM32MP1 implementation of this function will call
plat_report_exception(). It displays more information about the panic
if DEBUG is enabled.
The LR register is also filled with R6 content, which hold the faulty
address. This allows debugger to reconstruct the backtrace.

Change-Id: I6710e8e2ab6658b05c5bbad2f3c545f07f355afb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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stm32mp1: update plat_report_exception

In case DEBUG is enabled, plat_report_exception will now display extra
information of the cause of the exception.

Change-Id: I72cc9d180959cbf31c13821dd051eaf4

stm32mp1: update plat_report_exception

In case DEBUG is enabled, plat_report_exception will now display extra
information of the cause of the exception.

Change-Id: I72cc9d180959cbf31c13821dd051eaf4462b733e
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Align AARCH32 version of debug.S with AARCH64

Re-order code (put panic and report_exception at the end of the file).
Export asm_print_* functions.
Add asm_print_line_dec macro, and asm_print_newline

Align AARCH32 version of debug.S with AARCH64

Re-order code (put panic and report_exception at the end of the file).
Export asm_print_* functions.
Add asm_print_line_dec macro, and asm_print_newline func.
Align comments in both AARCH32 and AARCH64 files.
Add blank lines in AARCH64 files to align with AARCH32.

Change-Id: I8e299a27c1390f71f04e260cd4a0e59b2384eb19
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "n1sdp: add support for remote chip pcie." into integration

Merge "build_macros.mk: include assert and define loop macros" into integration

Merge "defaults.mk: default KEY_SIZE to 2048 in case of RSA algorithm" into integration

libc: Import strtok_r from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93
Sig

libc: Import strtok_r from FreeBSD project

From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b
Made small changes to fit into TF-A project

Change-Id: I991f653a7ace04f9c84bcda78ad8d7114ea18e93
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "ehf_common" into integration

* changes:
plat: tegra: Use generic ehf defines
ehf: use common priority level enumuration

Merge "spmd: remove assert for SPMC PC value" into integration

Merge "doc: Recommend using C rather than assembly language" into integration

n1sdp: add support for remote chip pcie.

Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.

Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sa

n1sdp: add support for remote chip pcie.

Remote chip ITS, SMMU, PCIe nodes are added for enabling remote
chip PCIe hierarchy.

Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>

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Merge "SPE: Fix feature detection" into integration

Merge changes from topic "cot-parser" into integration

* changes:
plat/arm: fvp: Increase BL2 maximum size
lib: fconf: Implement a parser to populate CoT

Merge "doc: Correct CPACR.FPEN usage" into integration

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
num

SPMC: adjust the number of EC context to max number of PEs

According to [1] and in context of FF-A v1.0 a secure partition must
have either one EC (migratable UP) or a number of ECs equal to the
number of PEs (pinned MP). Adjust the SPMC manifest such that the
number of ECs is equal to the number of PEs.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/components/
secure-partition-manager.html#platform-topology

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie8c7d96ae7107cb27f5b97882d8f476c18e026d4

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plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e

plat/arm: fvp: Increase BL2 maximum size

Increased BL2 maximum size when CoT descriptors are placed
in device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6466d2841e189e7f15eb4f1a8db070542893cb5b

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lib: fconf: Implement a parser to populate CoT

Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled

lib: fconf: Implement a parser to populate CoT

Implemented a parser which populates the properties of
the CoT descriptors as per the binding document [1].
'COT_DESC_IN_DTB' build option is disabled by default and can
be enabled in future for all Arm platforms by making necessary
changes in the memory map.
Currently, this parser is tested only for FVP platform.

[1]:
https://trustedfirmware-a.readthedocs.io/en/latest/components/cot-binding.html

Change-Id: I2f911206087a1a2942aa728de151d2ac269d27cc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "doc: add description of "owner" field in SP layout file." into integration

Merge changes from topic "sami/834_fiptool_pack_issue_win_v1" into integration

* changes:
Update makefile to build fiptool for Windows
Fix fiptool packaging issue on windows

doc: add description of "owner" field in SP layout file.

Change-Id: Iedaa83ed546eb2476849a8d53f6e05b847a48b23
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

Merge "fdts: corstone700: add NXP isp1763 node to device tree" into integration

Merge "rockchip: don't crash if we get an FDT we can't parse" into integration

SPE: Fix feature detection

Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any

SPE: Fix feature detection

Currently the feature test for the SPE extension requires the feature
bits in the ID_AA64DFR0 register to read exactly 0b0001.
However the architecture guarantees that any values greater than 0
indicate the presence of a feature, which is what we are after in
our spe_supported() function.

Change the comparison to include all values greater than 0.

This fixes SPE support in non-secure world on implementations which
include the Scalable Vector Extension (SVE), for instance on Zeus cores.

Change-Id: If6cbd1b72d6abb8a303e2c0a7839d508f071cdbe
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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