Merge "fdts: n1sdp: DTS file for single-chip and multi-chip environment." into integration

docs: marvell: update PHY porting layer description

The purpose of rx_training had changed after last update. Currently it
is not supposed to help with providing static parameters for porting
layer.

docs: marvell: update PHY porting layer description

The purpose of rx_training had changed after last update. Currently it
is not supposed to help with providing static parameters for porting
layer. Instead, it aims to suit the parameters per connection.

Change-Id: I2a146b71e2e20bd264c090a9a627d0b6bc56e052
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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docs: marvell: update path in marvell documentation

Change-Id: I0cebbaa900aa518700f13cbf02f8a97e0c76b21c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

docs: marvell: update build instructions with CN913x

Add references to the OcteonTX2 CN913x family.

Change-Id: I172a8e3d061086bf4843acad014c113c80359e01
Signed-off-by: Konstantin Porotchkin <kostap

docs: marvell: update build instructions with CN913x

Add references to the OcteonTX2 CN913x family.

Change-Id: I172a8e3d061086bf4843acad014c113c80359e01
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: octeontx: add support for t9130

CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
-

plat: marvell: octeontx: add support for t9130

CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
- on-board CP115 (MCI0)
- extension board CP115 (MCI1)

The board is based on DIMM DDR.

The 9130 has up to 3CP, and decoding windows looks like below:

(free for further use)
.----------. 0xf800 0000
| CP2 CFG |
'----------' 0xf600 0000
| CP1 CFG |
'----------' 0xf400 0000
| CP0 CFG |
'----------' 0xf200 0000
| AP CFG |
'----------' 0xf000 0000
(free for further use)
.----------. 0xec00 0000
| SPI |
| MEM_MAP | (Currently not opened)
'----------' 0xe800 0000
| PEX2_CP2 |
'----------' 0xe700 0000
| PEX1_CP2 |
'----------' 0xe600 0000
| PEX0-CP2 |
'----------'
.----------. 0xe500 0000
| PEX2_CP1 |
'----------' 0xe400 0000
| PEX1_CP1 |
'----------' 0xe300 0000
| PEX0-CP1 |
'----------'
.----------. 0xe200 0000
| PEX2-CP0 |
'----------' 0xe100 0000
| PEX1-CP0 |
'----------' 0xe000 0000
| PEX0-CP0 |
| 512MB |
'----------' 0xc000 0000

Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: t9130: add SVC support

As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.

Chan

plat: marvell: t9130: add SVC support

As the preparation for adding the CN913x SoC family support
introduce code that enable SVC and the frequency handling
specific for the AP807 North Bridge.

Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3
Signed-off-by: Alex Evraev <alexev@marvell.com>

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plat: marvell: t9130: update AVS settings

Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.

Change-Id: Ib1dd70885a316ed5763d0f4730d0e47

plat: marvell: t9130: update AVS settings

Update AVS settings and remove unused macros.
This is a preparation patch for adding CN913x SoC
family support.

Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: t9130: pass actual CP count for load_image

Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.

Cha

plat: marvell: t9130: pass actual CP count for load_image

Add CN913x case to bl2_plat_get_cp_count.
Fix loading of cp1/2 image. This is a preparation
patch for adding CN913x SoC family support.

Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9
Signed-off-by: Ben Peled <bpeled@marvell.com>

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plat: marvell: armada: a7k: add support to SVC validation mode

Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz

Change-Id: Ia72b10e0ccfad0756

plat: marvell: armada: a7k: add support to SVC validation mode

Add support for “AVS reduction” feature at this mode for
7040 Dual Cluster operation mode at CPU=1600MHz

Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2
Signed-off-by: Alex Evraev <alexev@marvell.com>

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plat: marvell: armada: add support for twin-die combined memory device

the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable comp

plat: marvell: armada: add support for twin-die combined memory device

the twin-die combined memory device should be treated as
X8 device and not as X16 one. This patch is required to
re-enable compilation after BLE (mv-ddr-marvell) firmware upgrade.

Change-Id: I41257ff2825164ebca85a84bbb8462d7b3447b97
Signed-off-by: Moti Buskila <motib@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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fdts: n1sdp: DTS file for single-chip and multi-chip environment.

N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilat

fdts: n1sdp: DTS file for single-chip and multi-chip environment.

N1SDP supports both single-chip and multi-chip environment.
Added DTS file for both type of environment.
Enabled DTS files compilation for N1SDP platform.

Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0
Co-authored-by: Robin Murphy <Robin.Murphy@arm.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com>
Co-authored-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>

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fconf: spm: minor bug fix

This patch fixes a bug where wrong panic was caused when the number
of SP was same as max limit.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9ace62d8

fconf: spm: minor bug fix

This patch fixes a bug where wrong panic was caused when the number
of SP was same as max limit.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I9ace62d8d5bcdc410eeacdd9d33d55a7be5fcc8e

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Merge "GIC-600: Fix MISRA-2012 defects" into integration

GIC-600: Fix MISRA-2012 defects

This patch fixes violation of Rules 10.1, 10.4,
11.9 and 13.2 reported by MISRA-2012 scan.

Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25
Signed-off-by: Alexei

GIC-600: Fix MISRA-2012 defects

This patch fixes violation of Rules 10.1, 10.4,
11.9 and 13.2 reported by MISRA-2012 scan.

Change-Id: Ibe9190cb0f26ae85d9a31db8e92fbd32f1740e25
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "docs/fvp: update SGI and RD FVP list" into integration

Aarch32 xlat_tables lib: Fix MISRA-2012 defects

This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
sta

Aarch32 xlat_tables lib: Fix MISRA-2012 defects

This patch fixes violation of Rules 2.1, 7.3, 10.1,
10.4, 12.1, 14.3, 14.4, 17.7, 20.9 reported by
MISRA-2012 scan and adds braces for conditional
statements according to the TF-A coding style.

Change-Id: Ib2463601fb43d955c3d901102b6dceaaad6614f3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "doc: secure partition manager design" into integration

Merge "Fix broken link in documentation" into integration

Merge "plat/nvidia: tegra: Enable SMCCC_ARCH_SOC_ID feature" into integration

Merge "plat/arm: Disable SMCCC_ARCH_SOC_ID feature" into integration

Merge "SMCCC: Introduce function to check SMCCC function availability" into integration

Fix broken link in documentation

The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception

Fix broken link in documentation

The link to the exception handling framework page on the System Design /
Firmware Design / Section 4.3 just links to itself, so I changed it to
link to the exception handling framework component document.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6711b423a789b2b3d1921671e8497fffa8ba33d1

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Merge "doc: use docker to build documentation" into integration

Merge "TZ DMC620 driver: Fix MISRA-2012 defects" into integration

TZ DMC620 driver: Fix MISRA-2012 defects

This patch fixes defects 10.3, 10.4, 10.7, 20.7
reported by MISRA-2012 scan and adds braces for
conditional statements according to the TF-A
coding style.

C

TZ DMC620 driver: Fix MISRA-2012 defects

This patch fixes defects 10.3, 10.4, 10.7, 20.7
reported by MISRA-2012 scan and adds braces for
conditional statements according to the TF-A
coding style.

Change-Id: If84ed31cdd55bc8e7cdd2a5f48c0dacc25792112
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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