Merge "Move static vars into functions in bl1" into integration

Merge "plat/arm: Get the base address of nv-counters from device tree" into integration

Merge "dtsi: Update the nv-counter node in the device tree" into integration

Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
Tegra: common: disable GICC after domain off
cpus: denver: skip DCO enable/disable for recent SKUs

Merge "Remove Jack Bond-Preston as CMake Build Definitions code owner" into integration

spmd: remove assert for SPMC PC value

This patch removes the assert that expects the SPMC PC
value to be same as BL32_BASE. This assumption is not
true for all platforms e.g. Tegra, and so will be r

spmd: remove assert for SPMC PC value

This patch removes the assert that expects the SPMC PC
value to be same as BL32_BASE. This assumption is not
true for all platforms e.g. Tegra, and so will be removed
from the SPMD.

Platforms can always add this check to the platform files,
if required.

Change-Id: Ic40620b43d160feb4f72f4af18e6d01861d4bf37
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "Add support to export a /cpus node to the device tree." into integration

Add support to export a /cpus node to the device tree.

This patch creates and populates the /cpus node in a device tree
based on the existing topology. It uses the minimum required nodes
and propert

Add support to export a /cpus node to the device tree.

This patch creates and populates the /cpus node in a device tree
based on the existing topology. It uses the minimum required nodes
and properties to satisfy the binding as specified in
https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0

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Merge "sp_min: Avoid platform security reconfiguration" into integration

Merge "doc: Update the cot-binding for nv-counter node" into integration

mediatek: Add jedec info

Add jedec info for mt8173, mt8183, and mt8192.

[1] http://www.softnology.biz/pdf/JEP106AV.pdf

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Change-Id: Iab36fd580131f0b

mediatek: Add jedec info

Add jedec info for mt8173, mt8183, and mt8192.

[1] http://www.softnology.biz/pdf/JEP106AV.pdf

Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Change-Id: Iab36fd580131f0b09b27223fba0e9d1e187d9196

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Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
Tegra: platform specific BL31_SIZE
Tegra186: sanity check power state type
Tegra: fixup CNTPS_TVAL_EL1 delay ti

Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
Tegra: platform specific BL31_SIZE
Tegra186: sanity check power state type
Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
Tegra: add platform specific 'runtime_setup' handler
Tegra: remove ENABLE_SVE_FOR_NS = 0
lib: cpus: denver: add MIDR PN9 variant
cpus: denver: introduce macro to declare cpu_ops

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spd: trusty: allow clients to retrieve service UUID

This patch implements support for the 64-bit and 32-bit versions of
0xBF00FF01 SMC function ID, as documented by the SMCCC, to allow
non-secure wo

spd: trusty: allow clients to retrieve service UUID

This patch implements support for the 64-bit and 32-bit versions of
0xBF00FF01 SMC function ID, as documented by the SMCCC, to allow
non-secure world clients to query SPD's UUID.

In order to service this FID, the Trusty SPD now increases the range
of SMCs that it services. To restrict Trusty from receiving the extra
SMC FIDs, this patch drops any unsupported FID.

Verified with TFTF tests for UID query and internal gtest for Trusty.

Change-Id: If96fe4993f7e641595cfe67cc6b4210a0d52403f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: common: fixup the bl31 code size to be copied at reset

If the CPU doesn't run from BL31_BASE, the firmware needs to be
copied from load address to BL31_BASE during cold boot. The size
should

Tegra: common: fixup the bl31 code size to be copied at reset

If the CPU doesn't run from BL31_BASE, the firmware needs to be
copied from load address to BL31_BASE during cold boot. The size
should be the actual size of the code, which is indicated by the
__RELA_END__ linker variable.

This patch updates the copy routine to use this variable as a
result.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9

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Tegra: common: disable GICC after domain off

The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU o

Tegra: common: disable GICC after domain off

The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU off sequence.

This patch disables the GICC after CPU off as a result.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea

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cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3a

cpus: denver: skip DCO enable/disable for recent SKUs

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-b

Tegra: platform specific BL31_SIZE

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

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Tegra186: sanity check power state type

This patch sanity checks the power state type before use,
from the platform's PSCI handler.

Verified with TFTF Standard Test Suite.

Change-Id: Icd45faac6c02

Tegra186: sanity check power state type

This patch sanity checks the power state type before use,
from the platform's PSCI handler.

Verified with TFTF Standard Test Suite.

Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fixup CNTPS_TVAL_EL1 delay timer reads

The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as

Tegra: fixup CNTPS_TVAL_EL1 delay timer reads

The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as an incrementing timer, by negating the timer value.

This patch fixes the anomaly and updates the driver to remove this logic.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4

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Tegra: add platform specific 'runtime_setup' handler

Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'r

Tegra: add platform specific 'runtime_setup' handler

Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.

Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

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Tegra: remove ENABLE_SVE_FOR_NS = 0

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but

Tegra: remove ENABLE_SVE_FOR_NS = 0

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but this flag can safely be enabled now that the
library can enable the feature at runtime.

This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0"
as a result.

Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

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lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani C

lib: cpus: denver: add MIDR PN9 variant

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3

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cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dca

cpus: denver: introduce macro to declare cpu_ops

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977

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Merge "qti: spmi_arb: Fix coverity integer conversion warnings" into integration

Move static vars into functions in bl1

This reduces the scope of these variables and resolves Misra violations
such as:
bl1/aarch64/bl1_context_mgmt.c:21:[MISRA C-2012 Rule 8.9 (advisory)]
"

Move static vars into functions in bl1

This reduces the scope of these variables and resolves Misra violations
such as:
bl1/aarch64/bl1_context_mgmt.c:21:[MISRA C-2012 Rule 8.9 (advisory)]
"bl1_cpu_context" should be defined at block scope.

Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I9b0b26395bce07e10e61d10158c67f9c22ecce44

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