Merge "fdt: Fix coverity complaint about 32-bit multiplication" into integration

fdt: Fix coverity complaint about 32-bit multiplication

Coverity raised an eyebrow over our GICR frame size calculation:
========
CID 362942: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Po

fdt: Fix coverity complaint about 32-bit multiplication

Coverity raised an eyebrow over our GICR frame size calculation:
========
CID 362942: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "nr_cores * gicr_frame_size" with type
"unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic,
and then used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).
========

Even with a GICv4 (256KB frame size) we need 16384 cores to overflow
32-bit, so it's not a practical issue.

But it's also easy to fix, so let's just do that: cast gicr_frame_size
to an unsigned 64-bit integer, so that the multiplication is done in the
64-bit realm.

Change-Id: Iad10e19b9e58d5fbf9d13205fbcef0aac5ae48af
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into integration

* changes:
Rename Neoverse Zeus to Neoverse V1
Rename Cortex Hercules AE to Cortex 78 AE

Merge "plat/arm: common: add guard for arm_get_rotpk_info_regs" into integration

Merge "doc: Update list of supported FVP platforms" into integration

plat/arm: common: add guard for arm_get_rotpk_info_regs

Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform buil

plat/arm: common: add guard for arm_get_rotpk_info_regs

Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform build without definition of TZ_PUB_KEY_HASH_BASE
if dedicated registers for ROTPK are not available on the platform.

Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7
Signed-off-by: Usama Arif <usama.arif@arm.com>

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Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration

* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive

Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration

* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711

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Merge "Workaround for Cortex A76 erratum 1868343" into integration

Rename Neoverse Zeus to Neoverse V1

Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Rename Cortex Hercules AE to Cortex 78 AE

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

docs: code review guidelines

Document the code review process in TF-A.
Specifically:

* Give an overview of code review and best practices.
* Give guidelines for the participants in code review.

docs: code review guidelines

Document the code review process in TF-A.
Specifically:

* Give an overview of code review and best practices.
* Give guidelines for the participants in code review.
* Outline responsibilities of each type of participant.
* Explain the Gerrit labels used in the review process.

Change-Id: I519ca4b2859601a7b897706e310f149a0c92e390
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: David Horstmann <david.horstmann@arm.com>

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bl32: add an assert on BL32_SIZE in sp_min.ld.S

This assert is present in all other linker scripts. This checks the
size of BL32 doesn't exceed its defined limit.

Change-Id: I0005959b5591d3eebd8700

bl32: add an assert on BL32_SIZE in sp_min.ld.S

This assert is present in all other linker scripts. This checks the
size of BL32 doesn't exceed its defined limit.

Change-Id: I0005959b5591d3eebd870045adafe437108bc9e1
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S

The macro SORT_BY_ALIGNMENT is used for .text* and .rodata*. This allows
reducing the space lost to object alignment. This is an alignment with
the f

bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S

The macro SORT_BY_ALIGNMENT is used for .text* and .rodata*. This allows
reducing the space lost to object alignment. This is an alignment with
the following patch:
ebd6efae67c6a086bc97d807a638bde324d936dc

Some comments are also aligned with other linker scripts.

Change-Id: I2ea59edb445af0ed8c08fd883ffbf56852570d0c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "doc: stm32mp1: Improve OP-TEE related documentation" into integration

docs: marvell: update mv_ddr branch

Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.

Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Si

docs: marvell: update mv_ddr branch

Now that the BLE image sources (mv_ddr) are updated, reflect
the proper branch in the Armada build howto.

Change-Id: I959d1343d0dfdd681c7e39bdcaed9b36aaddfca1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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plat: marvell: armada: a3k: rename the UART images archive

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot out

plat: marvell: armada: a3k: rename the UART images archive

Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.

Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: a3k: allow image load to RAM address 0

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking th

plat: marvell: armada: a3k: allow image load to RAM address 0

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.

Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re

marvell: comphy: cp110: add support for USB comphy polarity invert

The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.

Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe

marvell: comphy: cp110: add support for SATA comphy polarity invert

The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.

Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960c

marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353

According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should
be toggled in addition to the XFI/SFI PHY reset.

Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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drivers: marvell: mochi: Update AP incoming masters secure level

Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secur

drivers: marvell: mochi: Update AP incoming masters secure level

Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secure
SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not
changed when forwarded to address decoding tables.

Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: add ccu window for workaround errata-id 3033912

Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].

Change-Id: I63ee68338d674114d01cd627198

plat: marvell: armada: add ccu window for workaround errata-id 3033912

Added ccu window to allow access to addresses
in the range [0xf100_0000, 0xf1ff_ffff].

Change-Id: I63ee68338d674114d01cd627198dc907653493e8
Signed-off-by: Alex Leibovich <alexl@marvell.com>

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plat: marvell: ap806: implement workaround for errata-id FE-4265711

ERRATA ID: FE-4265711 - Incorrect CNTVAL reading

CNTVAL reflects the global system counter value in binary format.
Due to this er

plat: marvell: ap806: implement workaround for errata-id FE-4265711

ERRATA ID: FE-4265711 - Incorrect CNTVAL reading

CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.

Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.

Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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Merge "libfdt: Upgrade libfdt source files" into integration

Merge "spmd: Fix signedness comparison warning" into integration