Merge changes from topic "console_stm32" into integration

* changes:
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch32: remove unnecessary timeout

Merge changes from topic "console_stm32" into integration

* changes:
fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch32: remove unnecessary timeout waiting in putc
fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush
fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

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Merge "docs: ff-a manifest binding to document SPMC" into integration

docs: ff-a manifest binding to document SPMC

The FF-A manifest binding section was extended
to document the SPMC manifest as well.

The configuration is for the SPMD, which is common
to SPMC impleme

docs: ff-a manifest binding to document SPMC

The FF-A manifest binding section was extended
to document the SPMC manifest as well.

The configuration is for the SPMD, which is common
to SPMC implementations.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If8747a701212cedebc4a9dd66f2040443ce5e30f

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docs: ff-a manifest bindings for SP lifecycle support

This patch documents the manifest bindings for SP lifecycle support
as described in the FF-A v1.3 ALP2 specification.

Change-Id: I5d2e80520bc98

docs: ff-a manifest bindings for SP lifecycle support

This patch documents the manifest bindings for SP lifecycle support
as described in the FF-A v1.3 ALP2 specification.

Change-Id: I5d2e80520bc98c8e808da7d3204c2b4d91386536
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from

feat(spmd): support for FFA_ABORT invocation from SWd

SPMC can propagate abort handling to SPMD when an SP specifies suitable
abort action in its manifest. SPMD panics upon receiving FFA_ABORT from
SPMC.

Change-Id: I3b573fdfc203c3446b1d629f579e333162d5ff72
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(bl2): unify the BL2 EL3 and RME entrypoints

BL2 has 3(!) entrypoints:
1) the regular EL1 entrypoint (once per AArch)
2) an EL3 entrypoint
3) an EL3 entrypoint with RME

The EL1 and EL3 entryp

fix(bl2): unify the BL2 EL3 and RME entrypoints

BL2 has 3(!) entrypoints:
1) the regular EL1 entrypoint (once per AArch)
2) an EL3 entrypoint
3) an EL3 entrypoint with RME

The EL1 and EL3 entrypoints are quite distinct so it's useful to keep
them separate. But the EL3 and RME entrypoints are conceptually
identical just configured differently and having slightly different
assumptions (eg whether we can rely on BL1). So put them together with
only the configuration as a difference. This has a few benefits:
* makes the naming consistent - BL2 always runs at EL1, BL2_EL3 always
runs at EL3. This is most important for the linker script.
* paves the way for ENABLE_RME and RESET_TO_BL2 to coexist.
* allows for more general refactors

Currently, ENABLE_RME and RESET_TO_BL2 are mutually exclusive (from a
makefile constraint) so the checks are simplified to one or the other as
there is no danger of their simultaneous use.

Change-Id: Iecffab2ff3a0bd7823f8277d9f66e22e4f42cc8c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I

fix(st-uart): aarch32: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.

Change-Id: I94b6238e3f8a94bc4a1fabaf8d45d3b66d42e834
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
compl

fix(st-uart): aarch32: remove unnecessary timeout waiting in putc

The UART is configured with FIFO enabled, therefore putting a
character in the TDR register and wait for the transmission flag
complete is enough.

Change-Id: I5e254df89f2652e300ea5bedf9269d420895bdbf
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the retur

fix(st-uart): aarch64: wait for UART ISR register TC bit for console flush

Loop over the UART_ISR_TC bit to make sure the FIFO is emptied and all
the data is out of the shift register.
Fix the return value that should be void in flush related functions
description.

Change-Id: Idbeecc3ca36b6ce506c9489b4f611bbe345121a3
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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Merge "fix(xilinx): typecast operands to match data type" into integration

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entr

feat(spmd): get spmc manifest from xferlist

When TRANSFER_LIST build option is used, arg0 doesn't pass the
SPMC manifest. but it should be passed to load SPMC.

For this, adds the spmc manifest entry in the transfer list
with TL_TAG_DT_SPMC_MANIFEST tag and
let spmd load the spmc manifest from transfer list.

Change-Id: I3b84c3d8a17bba4ac94afe00e1e19044449360b0
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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Merge "fix(smccc): resolve caller world confusion" into integration

Merge "feat(rcar): add support for Renesas R-Car S4 / V4H / V4M" into integration

refactor(lib): add cache unit alignment attribute to cpu_context_t

This patch ensures that the dirty cache lines associated with a single
CPU's context are contained within that core, preventing the

refactor(lib): add cache unit alignment attribute to cpu_context_t

This patch ensures that the dirty cache lines associated with a single
CPU's context are contained within that core, preventing them from
being shared with other CPUs. The alignment applied to cpu_context_t
is consistent with the existing alignment for cpu_data_t.

Change-Id: I4973cd46fe85724f61cd83e4d26ec366671061e2
Signed-off-by: Noah Woo <namyoon@google.com>

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fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character w

fix(st-uart): aarch64: unwait for UART ISR register TC bit in putc function

The loop over the UART_ISR_TC flag was needed before the UART FIFO was
enabled. This allowed to make sure each character written in TDR was
outputed.
This behavior is no more needed. Once a character is in the FIFO the
UART will empty it when it is clocked.

Change-Id: I914c7f75a451bedbcc9287d8ed9178db47b4eab4
Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com>

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feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU p

feat(rcar): add support for Renesas R-Car S4 / V4H / V4M

Add support for Renesas R-Car S4 / V4H / V4M , which are Gen4 SoC.
Add platform code, BL31 setup code, platform specific PSCI handlers,
CPU power driver, Gen4 (H)SCIF driver, and function to get canary for
stack protector. Unlike Gen3, the Gen4 uses only TFA BL31 during boot.

Change-Id: Ic0eb8638a85757f997f29fc524c118c3e5d5135a
Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.dn@renesas.com>
Signed-off-by: Jing Dan <jing.dan.nx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Masashi Ozaki <masashi.ozaki.te@renesas.com>
Signed-off-by: Taichiro Yokoyama <taichiro.yokoyama.ns@hitachi.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Tsukasa Kawaguchi <tsukasa.kawaguchi.aw@hitachi.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Vincent Bryce <vincent.bryce@cogentembedded.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
---
NOTE: This patch is squashed and cleaned up from large stack of patches
from multiple authors. SoB line from each author is included here,
the author of this commit is set to myself although that is most
certainly not accurate.

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Merge "feat(spmd): add FFA_NS_RES_INFO_GET ABI" into integration

Merge "feat(el3-spmc): parse and report VM availability messages" into integration

Merge changes from topic "rmm-lfa" into integration

* changes:
feat(rmmd): add RMM_RESERVE_MEMORY SMC handler
feat(rmmd): add per-CPU activation token

feat(versal): add support to clear PM specific data

During a kexec restart, only the kernel is reloaded while TF-A state
remains unchanged, causing a mismatch between kernel and TF-A states.
To reso

feat(versal): add support to clear PM specific data

During a kexec restart, only the kernel is reloaded while TF-A state
remains unchanged, causing a mismatch between kernel and TF-A states.
To resolve this, add support for the TF_A_CLEAR_PM_STATE API, which
clears TF-A PM state.

Change-Id: I6b460f8cd4293381d3a9c574dd144521b8e54f8a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_

fix(versal-net): fix coverity violation prevent buffer overrun

Coverity reported potential memory corruption issues in
bl31_early_platform_setup2() (CIDs 487973 and 487972):

- CID 487973 (ARRAY_VS_SINGLETON): "&boot_mode" was passed to
get_boot_mode(), which treats the argument as an array. This could
lead to misinterpretation of adjacent memory.
- CID 487972 (OVERRUN): Passing "&boot_mode" (a single 4-byte element)
allowed get_boot_mode() to access out-of-bounds indices, resulting in
a possible buffer overrun.

Changed boot_mode from a single variable to an array sized according
to the return payload, preventing singleton pointer violation.

Change-Id: I53944db10b694d1599da0e5b1fbd30a97e83803c
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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docs(tegra): add note that clang is not supported

This has never worked. Since the general docs indicate that clang is
supported, the Tegra docs should explicitly state that it is not
supported.

Ch

docs(tegra): add note that clang is not supported

This has never worked. Since the general docs indicate that clang is
supported, the Tegra docs should explicitly state that it is not
supported.

Change-Id: I07654e02717a1a53a5d64088f4a79b034030bf26
Signed-off-by: Aaron Kling <webgeek1234@gmail.com>

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feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some

feat(rmmd): add RMM_RESERVE_MEMORY SMC handler

At the moment any memory required by an R-EL2 manager (RMM) needs to
be known at compile time: that sets the size of the .data and .bss
segments. Some resources depend on the particular machine this will be
running on, the prime example is TF-RMM's granule array, which needs to
know the maximum memory supported beforehand. Other data structures
might depend on the number of CPU cores.

To provide more flexibility, but keep the memory footprint as small as
possible, let's introduce some memory reservation SMC. Any RMM
implementation can ask EL3 for some memory, and would get the physical
address of a usable chunk of memory back. This must happen at RMM boot
time, so before the RMM concluded the boot phase with the
RMM_BOOT_COMPLETE SMC call. Also there is no provision to free memory
again, this would not be needed for the use case of sizing platform
resources, and avoids the complexity of a full-fledged memory allocator.

Add the new RMM_RESERVE_MEMORY command to the implementation defined
RMM-EL3 SMC interface, both in code and documentation. The actual memory
reservation is made a platform implementation, but a simple
implementation is provided, which is used for the FVP platform already:
it will just pick the next matching chunk of memory from the top end of
the RMM carveout. This way the memory reservation will grow down from
the end of the carveout, in a stack-like fashion, until it reaches the
end of the RMM payload, located at the beginning of the carveout. Since
secondary cores might also reserve memory at boot time, there is a
spinlock to protect the simple allocation algorithm.
Other platforms can choose to provide a more sophisticated reservation
algorithm, for instance one taking NUMA locality into account.

This patch just provides the call, at this point there is no obligation
to use the feature, although future TF-RMM versions would rely on it.

Change-Id: I096ac8870ee38f44e18850779fcae829a43a8fd1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(rmmd): add per-CPU activation token

To accommodate Live Firmware Activation (LFA), the RMM needs to preserve
some state, between an old and the new copy of itself.
The state which needs to be p

feat(rmmd): add per-CPU activation token

To accommodate Live Firmware Activation (LFA), the RMM needs to preserve
some state, between an old and the new copy of itself.
The state which needs to be preserved and its organisation would be
completely under control of the RMM; it will be different between
different RMM implementations and even between releases.

To keep the interface small, generic and robust, introduce an
"activation token", which is an opaque 64-bit value to gets passed to
each RMM as part of the boot/init phase. On the first initialisation,
after a cold boot, this value would be initialised to 0. The RMM is
expected to pass the actual value (for instance a pointer to a
persistent data structure) back to BL31 as an additional argument of the
RMM_BOOT_COMPLETE SMC call. On subsequent live activations, this updated
token value gets passed to the (updated) RMM init routines, using the
respective CPU registers.

Add an activation_token member to the (per-CPU) RMM context, and update
its value with the value passed via the x2 register, at the
RMM_BOOT_COMPLETE SMC call. Then pass that value into RMM either via x4
(on the primary core) or via x1 (on secondary cores). How the value is
used or updated on the RMM side is of no further concern to BL31, it
just passes the opaque value around.
The TRP seems to be very jealous about the values in the first three
registers, so let it ignore the value of x1 on a warmboot, to avoid a
panic.

Change-Id: Ie8d96a046b74adb00e2ca5ce3b8458465bacf2b2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I5fcf6578,Ic7792603 into integration

* changes:
fix(xilinx): fix missing security flag in suspend path
feat(zynqmp): mark IPI calls secure/non-secure