Merge "TF-A: Add build option for Arm Feature Modifiers" into integration

Merge changes from topic "rdevans" into integration

* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in mem

Merge changes from topic "rdevans" into integration

* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping

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Add support for FEAT_MTPMU for Armv8.6

If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happ

Add support for FEAT_MTPMU for Armv8.6

If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.

If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.

This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e

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TF-A: Add build option for Arm Feature Modifiers

This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults t

TF-A: Add build option for Arm Feature Modifiers

This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.

Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before aut

plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989

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plat: zynqmp: Check for DLL status before doing reset

This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL rese

plat: zynqmp: Check for DLL status before doing reset

This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL reset will be issued.
By doing this way, all the following cases will be supported.
1. Patched ATF + Patched Linux base.
2. Older ATF + Patched Linux base.
3. Patched ATF + Older Linux base.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I53a0a27521330f1543275cc9cb44cd1dfc569c65

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Merge "xilinx: versal: fix static failure" into integration

xilinx: versal: fix static failure

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Icef550072296d6aba89a0827dd72d0b86047556f

Merge changes from topic "versal-bug-fixes-and-new-apis" into integration

* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate va

Merge changes from topic "versal-bug-fixes-and-new-apis" into integration

* changes:
plat: xilinx: versal: Add support of register notifier
plat: xilinx: versal: Add support to get clock rate value
plat: xilinx: versal: Add support of set max latency for the device
plat: versal: Add InitFinalize API call
xilinx: versal: Updated Response of QueryData API call
plat:xilinx:versal: Use defaults when PDI is without sw partitions
plat: xilinx: Mask unnecessary bytes of return error code
xilinx: versal: Skip store/restore of GIC during CPU idle
plat: versal: Update API list in feature check
xilinx: versal: Do not pass ACPU0 always in set_wakeup_source()

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Merge changes from topic "secure_no_primary" into integration

* changes:
spm: provide number of vCPUs and VM size for first SP
spm: remove chosen node from SPMC manifests
spm: move OP-TEE SP m

Merge changes from topic "secure_no_primary" into integration

* changes:
spm: provide number of vCPUs and VM size for first SP
spm: remove chosen node from SPMC manifests
spm: move OP-TEE SP manifest DTS to FVP platform
spm: update OP-TEE SP manifest with device-regions node
spm: remove device-memory node from SPMC manifests

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Merge "docs: Update the FIP generation process using SP images" into integration

docs: Update the FIP generation process using SP images

Updated the documentation for the FIP generation process using
SP images.

Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by:

docs: Update the FIP generation process using SP images

Updated the documentation for the FIP generation process using
SP images.

Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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doc: Update list of supported FVP platforms

Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi

doc: Update list of supported FVP platforms

Updated the list of supported FVP platforms with support for RD-N2 FVP.

Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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board/rdn2: add board support for rdn2 platform

Add the initial board support for RD-N2 platform.

Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@ar

board/rdn2: add board support for rdn2 platform

Add the initial board support for RD-N2 platform.

Change-Id: I8325885bf248dd92191d6fc92a2da91c23118f8c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: adapt to changes in memory map

Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping

plat/arm/sgi: adapt to changes in memory map

Upcoming RD platforms will have an updated memory map for the various
pheripherals on the system. So, for the newer platforms, handle the
memory mapping and other platform specific functionality separately
from the existing platforms.

Change-Id: Iab1355a4c8ea1f6db4f79fcdd6eed907903b6a18
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: add platform id value for rdn2 platform

In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info fo

plat/arm/sgi: add platform id value for rdn2 platform

In preparation for adding the board support for RD-N2 platform, add
macros to define the platform id and the corresponding SCMI platform
info for the RD-N2 platform.

Change-Id: Ie764ae618732b39e316f7ed080421f5d79adab21
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: platform definitions for upcoming platforms

Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
u

plat/arm/sgi: platform definitions for upcoming platforms

Upcoming RD platforms have changes in the SOC address map from that
of the existing platforms. As a prepartory step to add support for the
upcoming platforms, create platform definitions for those platforms.

Change-Id: Ic5df9fed02c44e65ec260bbb5efc1b8dbd919a56
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: refactor header file inclusions

Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support

plat/arm/sgi: refactor header file inclusions

Upcoming RD platforms have deviations in various definitions of
platform macros from that of the exisiting platforms. In preparation
for adding support for those upcoming RD platforms, refactor the
header file inclusion to allow newer platforms to use a different
set of platform macros.

Change-Id: Ic80283ddadafaa7f766f300652cb0d4e507efdb6
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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plat/arm/sgi: refactor the inclusion of memory mapping

Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
us

plat/arm/sgi: refactor the inclusion of memory mapping

Upcoming RD platforms have a different memory map from those of the
existing platforms. So make the build of the existing mmap entries to be
usable only for existing platforms and let upcoming platforms define
a different set of mmap entries.

Change-Id: Id1ef0293efe8749c78a99237e78d32573c7233aa
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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Merge "rcar_gen3: drivers: console: Treat log as device memory" into integration

Merge changes from topic "zynqmp-bug-fixes" into integration

* changes:
zynqmp: pm: Update flags in common clk divisor node
zynqmp: pm_api_clock: Copy only the valid bytes

rcar_gen3: drivers: console: Treat log as device memory

The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can

rcar_gen3: drivers: console: Treat log as device memory

The BL31 log driver is registered before the xlat tables are initialized,
at that point the log memory is configured as device memory and can only
be accessed with up-to-32bit aligned accesses. Adjust the driver to do
just that.

The memset() call has to be replaced by a loop of 32bit writes to the log,
the memcpy() is trivial to replace with a single 32bit write of the entire
TLOG word. In the end, this even simplifies the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie9152e782e67d93e7236069a294df812e2b873bf

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zynqmp: pm: Update flags in common clk divisor node

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does

zynqmp: pm: Update flags in common clk divisor node

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
Consider a case of nand_ref clock which has 2 divisor and 1 mux.
The frequency of mux clock is 1500MHz and default value of div1 and
div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
When driver requests 80MHz for nand_ref clock, clock framework will
adjust the div2 value to 1 (setting div2 value 2 results final clock
to 50MHz which is more inaccurate compare to 100Mhz) which results
final clock to 100MHz.
Ideally the value of div1 and div2 should be updated to 19 and 1
respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58

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zynqmp: pm_api_clock: Copy only the valid bytes

This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@

zynqmp: pm_api_clock: Copy only the valid bytes

This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7

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Merge changes Ibbee37c8,Ic3a13c83,Ib7f2380a,I83b477fd,I284956d4, ... into integration

* changes:
mediatek: mt8192: dcm: Add mcusys related dcm drivers
mediatek: mt8192: add ptp3 driver
mediate

Merge changes Ibbee37c8,Ic3a13c83,Ib7f2380a,I83b477fd,I284956d4, ... into integration

* changes:
mediatek: mt8192: dcm: Add mcusys related dcm drivers
mediatek: mt8192: add ptp3 driver
mediatek: mt8192: Add SiP service
mediatek: mt8192: add uart save and restore api
mediatek: mt8192: modify sys_cirq driver
mediatek: mt8192: add power-off support
mediatek: mt8192: add pmic mt6359p driver
mediatek: mt8192: Initialize delay_timer
mediatek: mt8192: enable NS access for systimer
mediatek: mt8192: Add CPU hotplug and MCDI support
mediatek: mt8192: Add MCDI drivers
mediatek: mt8192: Add SPMC driver

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