Merge "nxp: added the makefile helper macros" into integration

nxp: added the makefile helper macros

NXP specifc macro SET_NXP_MAKE_FLAG is added.

NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be i

nxp: added the makefile helper macros

NXP specifc macro SET_NXP_MAKE_FLAG is added.

NXP has pool of multiple IPs. This macro helps:
- In soc.mk, this macro help the selected IP source files to be included
for that SoC.
-- The set of IPs required for one NXP SoC is different to the set of IPs
required by another NXP SoC.

- For the same SoC,
-- For one feature, the IP may be required in both BL2 and BL31.
-- Without the above feature, that IP may be required in one.
This macro help in selecting the inclusion of source and header files to:
--- BL2 only
--- BL31 only
--- COMM (used by BL2 and BL31)

Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cdb13b89aa815fc5219cf8bfb9666d0a9f78765

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spmd: ensure SIMD context is saved/restored on SPMC entry/exit

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I8ed58ec5f97e05d91451020a2739464bb8e428b3

Merge "plat/arm: juno: Refactor juno_getentropy()" into integration

Merge "bl32: Enable TRNG service build" into integration

Merge "plat/arm/rdn2: update TZC base address" into integration

nand: stm32_fmc_nand: remove dead code

The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was

nand: stm32_fmc_nand: remove dead code

The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was found by Coverity scan: CID 366361.

Change-Id: I864c51ce11b9ef74ad82b3301f56f46a2e0f70ca
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge changes from topic "mp/strto_libc" into integration

* changes:
libc: Import strtoull from FreeBSD project
libc: Import strtoll from FreeBSD project
libc: Import strtoul from FreeBSD proj

Merge changes from topic "mp/strto_libc" into integration

* changes:
libc: Import strtoull from FreeBSD project
libc: Import strtoll from FreeBSD project
libc: Import strtoul from FreeBSD project
libc: Import strtol from FreeBSD project

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Merge "morello: Modify morello_plat_info structure" into integration

plat/arm: juno: Refactor juno_getentropy()

Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we w

plat/arm: juno: Refactor juno_getentropy()

Currently we use the Juno's TRNG hardware entropy source to initialise
the stack canary. The current function allows to fill a buffer of any
size, but we will actually only ever request 16 bytes, as this is what
the hardware implements. Out of this, we only need at most 64 bits for
the canary.

In preparation for the introduction of the SMCCC TRNG interface, we
can simplify this Juno specific interface by making it compatible with
the generic one: We just deliver 64 bits of entropy on each call.
This reduces the complexity of the code. As the raw entropy register
readouts seem to be biased, it makes sense to do some conditioning
inside the juno_getentropy() function already.
Also initialise the TRNG hardware, if not already done.

Change-Id: I11b977ddc5417d52ac38709a9a7b61499eee481f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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bl32: Enable TRNG service build

The Trusted Random Number Generator service is using the standard SMC
service dispatcher, running in BL31. For that reason we list the files
implementing the service

bl32: Enable TRNG service build

The Trusted Random Number Generator service is using the standard SMC
service dispatcher, running in BL31. For that reason we list the files
implementing the service in bl31.mk.
However when building for a 32-bit TF-A runtime, sp_min.mk is the
Makefile snippet used, so we have to add the files into there as well.

This fixes 32-bit builds of platforms that provide the TRNG service.

Change-Id: I8be61522300d36477a9ee0a9ce159a140390b254
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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include/drivers/marvell/mochi: add detection of secure mode

Change-Id: I99afc312617df86ae68eb30302203a03877ca748
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git

include/drivers/marvell/mochi: add detection of secure mode

Change-Id: I99afc312617df86ae68eb30302203a03877ca748
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/22541
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

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plat/marvell: fix SPD handling in dram port

The DRAM port code issues a dummy write to SPD page-0 i2c address
in order to select this page for the forthcoming read transaction.
If the write buffer l

plat/marvell: fix SPD handling in dram port

The DRAM port code issues a dummy write to SPD page-0 i2c address
in order to select this page for the forthcoming read transaction.
If the write buffer length supplied to i2c_write is not zero, this
call is translated to 2 bus transations:

- set the target offset
- write the data to the target

However no actual data should be transferred to SPD page-0 in order
to select it. Actually, the second transation never receives an ACK
from the target device, which caused the following error report:

ERROR: Status 30 in write transaction

This patch sets the buffer length in page-0 select writes to zero,
leading to bypass the data transfer to the target device.
Issuing the target offset command to SPD page-0 address effectively
selects this page for the read operation.

Change-Id: I4bf8e8c09da115ee875f934bc8fbc9349b995017
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/24387
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Moti Buskila <motib@marvell.com>

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marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1

Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address
space only and using this window bypasses the need for translation
in the SMMU

marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1

Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address
space only and using this window bypasses the need for translation
in the SMMU which has performance impact.

Change-Id: I98d99da59e904e6721cfa263ce44ad178a0fa956
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20389
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers/marvell/mochi: add support for cn913x in PCIe EP mode

Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1g

drivers/marvell/mochi: add support for cn913x in PCIe EP mode

Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20453
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>

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drivers/marvell/mochi: add missing stream IDs configurations

- Add setup of DMA stream IDs in AP807/AP806 drivers

Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Poro

drivers/marvell/mochi: add missing stream IDs configurations

- Add setup of DMA stream IDs in AP807/AP806 drivers

Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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plat/marvell/armada/a8k: support HW RNG by SMC

Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR suppo

plat/marvell/armada/a8k: support HW RNG by SMC

Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>

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drivers/rambus: add TRNG-IP-76 driver

Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs

Change-Id: I9c5f51

drivers/rambus: add TRNG-IP-76 driver

Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs

Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>

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plat/arm/rdn2: update TZC base address

Update TZC base address to align with the recent changes in the platform
memory map.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.c

plat/arm/rdn2: update TZC base address

Update TZC base address to align with the recent changes in the platform
memory map.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I0d0ad528a2e236607c744979e1ddc5c6d426687a

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Merge "services: TRNG: Fix -O0 compilation" into integration

services: TRNG: Fix -O0 compilation

The code to check for the presence of the TRNG service relies on
toolchain garbage collection, which is not enabled with -O0.

Add #ifdef guards around the call t

services: TRNG: Fix -O0 compilation

The code to check for the presence of the TRNG service relies on
toolchain garbage collection, which is not enabled with -O0.

Add #ifdef guards around the call to the TRNG service handler to
cover builds without optimisation as well.

Change-Id: I08ece2005ea1c8fa96afa13904a851dec6b24216
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "GIC-work" into integration

* changes:
plat/arm: fvp: Protect GICR frames for fused/unused cores
doc: Build option to protect GICR frame
plat/arm: fvp: Do not map GIC

Merge changes from topic "GIC-work" into integration

* changes:
plat/arm: fvp: Protect GICR frames for fused/unused cores
doc: Build option to protect GICR frame
plat/arm: fvp: Do not map GIC region in BL1 and BL2

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plat/arm: fvp: Protect GICR frames for fused/unused cores

Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.

This opens up the security hole where the active c

plat/arm: fvp: Protect GICR frames for fused/unused cores

Currently, BLs are mapping the GIC memory region as read-write
for all cores on boot-up.

This opens up the security hole where the active core can write
the GICR frame of fused/inactive core. To avoid this issue, disable
the GICR frame of all inactive cores as below:

1. After primary CPU boots up, map GICR region of all cores as
read-only.
2. After primary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
3. After secondary CPU boots up, map its GICR region as read-write
and initialize its redistributor interface.
4. All unused/fused core's redistributor regions remain read-only and
write attempt to such protected regions results in an exception.

As mentioned above, this patch offers only the GICR memory-mapped
region protection considering there is no facility at the GIC IP
level to avoid writing the redistributor area.

These changes are currently done in BL31 of Arm FVP and guarded under
the flag 'FVP_GICR_REGION_PROTECTION'.

As of now, this patch is tested manually as below:
1. Disable the FVP cores (core 1, 2, 3) with core 0 as an active core.
2. Verify data abort triggered by manually updating the ‘GICR_CTLR’
register of core 1’s(fused) redistributor from core 0(active).

Change-Id: I86c99c7b41bae137b2011cf2ac17fad0a26e776d
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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doc: Build option to protect GICR frame

Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a

doc: Build option to protect GICR frame

Added a build option 'FVP_GICR_REGION_PROTECTION' to make
redistributor frame of fused/unused cores as read only.

Change-Id: Ie85f86e2465b93321a92a888ce8712a3144e4ccb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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plat/arm: fvp: Do not map GIC region in BL1 and BL2

GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memor

plat/arm: fvp: Do not map GIC region in BL1 and BL2

GIC memory region is not getting used in BL1 and BL2.
Hence avoid its mapping in BL1 and BL2 that freed some
page table entries to map other memory regions in the
future.

Retains mapping of CCN interconnect region in BL1 and BL2
overlapped with the GIC memory region.

Change-Id: I880dd0690f94b140e59e4ff0c0d436961b9cb0a7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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