zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse

This patch adds new api to access zynqmp efuse memory

Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.

zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse

This patch adds new api to access zynqmp efuse memory

Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I0971ab6549552a6f96412431388d19b822db00ab

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zynqmp : pm : Adds new zynqmp-pm api SMC call for register access

This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.

Signed-off-by: Kalyani Akula <kalyan

zynqmp : pm : Adds new zynqmp-pm api SMC call for register access

This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.

Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042

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Merge "marvell: uart: a3720: Implement console_a3700_core_flush" into integration

Plat AXG: Fix PLAT_MAX_PWR_LVL value

This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript

Plat AXG: Fix PLAT_MAX_PWR_LVL value

This patch fixes AXG platform build error:
plat/amlogic/axg/axg_pm.c: In function 'axg_pwr_domain_off':
plat/amlogic/axg/axg_pm.c:124:43: error: array subscript 2
is above array bounds of 'const plat_local_state_t[2]'
{aka 'const unsigned char[2]'}
by changing PLAT_MAX_PWR_LVL from MPIDR_AFFLVL1 to MPIDR_AFFLVL2
in plat\amlogic\axg\include\platform_def.h.

Change-Id: I9a701e8f26231e62f844920aec5830664f3fb324
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration

* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite d

Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration

* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
ti: k3: Move USE_COHERENT_MEM only for the generic board
ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ti: k3: common: Enable A72 erratum 1319367
ti: k3: common: Enable A53 erratum 1530924
maintainers: Update maintainers for TI port

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marvell: uart: a3720: Implement console_a3700_core_flush

Implementation is simple, just wait for the TX FIFO to be empty.

Without this patch TF-A on A3720 truncate the last line:

NOTICE: BL31:

marvell: uart: a3720: Implement console_a3700_core_flush

Implementation is simple, just wait for the TX FIFO to be empty.

Without this patch TF-A on A3720 truncate the last line:

NOTICE: BL31: Built : 16:1

With this patch TF-A on A3720 print correctly also the last line:

NOTICE: BL31: Built : 19:03:31, Dec 23 2020

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2f2ea42beab66ba132afdb400ca7898c5419db09

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ti: k3: Introduce lite device board support

Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.

Note: This family of dev

ti: k3: Introduce lite device board support

Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.

Note: This family of devices are characterized by a single cluster
of ARMv8 processor upto a max of 4 processors and lack of a level 3
cache.

The first generation of this family is introduced with AM642.

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a

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ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition

There are two communication scheme that have been enabled to communicate
with Secure Proxy in TI.
a) A full fledged prioritized communi

ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition

There are two communication scheme that have been enabled to communicate
with Secure Proxy in TI.
a) A full fledged prioritized communication scheme, which involves upto
5 threads from the perspective of the host software
b) A much simpler "lite" version which is just a two thread scheme
involving just a transmit and receive thread scheme.

The (a) system is specifically useful when the SoC is massive
involving multiple processor systems and where the potential for
priority inversion is clearly a system usecase killer. However, this
comes with the baggage of significant die area for larger number of
instances of secure proxy, ring accelerator and backing memories
for queued messages. Example SoCs using this scheme would be:
AM654[1], J721E[2], J7200[3] etc.

The (b) scheme(aka the lite scheme) is introduced on smaller SoCs
where memory and area concerns are paramount. The tradeoff of
priority loss is acceptable given the reduced number of processors
communicating with the central system controller. This brings about
a very significant area and memory usage savings while the loss of
communication priority has no demonstrable impact. Example SoC using
this scheme would be: AM642[4]

While we can detect using JTAG ID and conceptually handle things
dynamically, adding such a scheme involves a lot of unused data (cost
of ATF memory footprint), pointer lookups (performance cost) and still
due to follow on patches, does'nt negate the need for a different
build configuration. However, (a) and (b) family of SoCs share the
same scheme and addresses etc, this helps minimize our churn quite a
bit

Instead of introducing a complex data structure lookup scheme, lets
keep things simple by first introducing the pieces necessary for an
alternate communication scheme, then introduce a second platform
representing the "lite" family of K3 processors.

NOTE: This is only possible since ATF uses just two (secure) threads
for actual communication with the central system controller. This is
sufficient for the function that ATF uses.

The (a) scheme and the (b) scheme also varies w.r.t the base addresses
used, even though the memory window assigned for them have remained
consistent. We introduce the delta as part of this change as well.
This is expected to remain consistent as a standard in TI SoCs.

References:
[1] See AM65x Technical Reference Manual (SPRUID7, April 2018)
for further details: https://www.ti.com/lit/pdf/spruid7

[2] See J721E Technical Reference Manual (SPRUIL1, May 2019)
for further details: https://www.ti.com/lit/pdf/spruil1

[3] See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

[4] See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I697711ee0e6601965015ddf950fdfdec8e759bfc

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ti: k3: Move USE_COHERENT_MEM only for the generic board

commit 65f7b81728d0 ("ti: k3: common: Use coherent memory for shared data")
introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to h

ti: k3: Move USE_COHERENT_MEM only for the generic board

commit 65f7b81728d0 ("ti: k3: common: Use coherent memory for shared data")
introduced WARMBOOT_ENABLE_DCACHE_EARLY and USE_COHERENT_MEM to handle
multiple clusters across L3 cache systems. This is represented by
"generic" board in k3 platform.

On "lite" platforms, however, system level coherency is lacking since
we don't have a global monitor or an L3 cache controller. Though, at
a cluster level, ARM CPU level coherency is very much possible since
the max number of clusters permitted in lite platform configuration is
"1".

However, we need to be able to disable USE_COHERENT_MEM for the lite
configuration due to the lack of system level coherency.

See docs/getting_started/build-options.rst for further information.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4a0ec150b3f9ea12369254aef834a6cbe82d6be6

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ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain

The ti_sci_msg_req_reboot message payload has been extended to include
a domain field, and this should be zero to reset the en

ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain

The ti_sci_msg_req_reboot message payload has been extended to include
a domain field, and this should be zero to reset the entire SoC with
System Firmwares newer than v2020.04. Add the domain field to the
ti_sci_msg_req_reboot message structure for completeness. Set it up
to zero to fix the reboot issues with newer firmwares.

This takes care of the specific ABI that changed and has an impact on
ATF function.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I4f8064b9d6555687822dc2b2b8ec97609286fa0b

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ti: k3: common: sec_proxy: Fill non-message data fields with 0x0

Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit
of a ch

ti: k3: common: sec_proxy: Fill non-message data fields with 0x0

Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit
of a challenge.

The backing memory for sec_proxy is regular memory, and all sec proxy
does is to trigger a burst of all 60 bytes of data over to the target
thread backing ring accelerator. It doesn't do a memory scrub when
it moves data out in the burst. When we transmit multiple messages,
remnants of previous message is also transmitted which results in
some random data being set in TISCI fields of messages that have been
expanded forward.

The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.

So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).

This allows us to scale and introduce ABI changes back into TF-A only
as needed.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ie22cb2a319f4aa80aef23ffc7e059207e5d4c640

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ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg

ARM's generic timer[1] picks up it's graycode from GTC. However, the
frequency of the GTC is supposed to be programmed in CNTFID0[2]

ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg

ARM's generic timer[1] picks up it's graycode from GTC. However, the
frequency of the GTC is supposed to be programmed in CNTFID0[2]
register.

In K3, architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based bootloader enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller, and TF-A is
supposed to use that as the frequency for it's local timer.

A mismatch in programmed frequency and what we program for generic
timer will, as we can imagine, all kind of weird mayhem.

So, check the CNTFID0 register, if it is 0, warn and use the default
frequency to continue the boot process.

While at it, we can also check CNTCR register to provide some basic
diagnostics to make sure that we don't have OS folks scratch their
heads. Even though this is used during cpu online operations, the cost
of this additional check is minimal enough for us not to use #ifdeffery
with DEBUG flags.

[1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary
[2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0
[3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ib03e06788580f3540dcb1a11677d0d6d398b2c9f

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ti: k3: common: Enable A72 erratum 1319367

The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72
platforms as well.

See the following for further information:
https://developer.arm.com/docu

ti: k3: common: Enable A72 erratum 1319367

The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72
platforms as well.

See the following for further information:
https://developer.arm.com/documentation/epm012079/11/

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I80c6262b9cdadcb12f6dfd5a21272989ba257719

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ti: k3: common: Enable A53 erratum 1530924

The CatB erratum ARM_ERRATA_A53_1530924 applies to all TI A53
platforms as well.

See the following for further information:
https://developer.arm.com/docu

ti: k3: common: Enable A53 erratum 1530924

The CatB erratum ARM_ERRATA_A53_1530924 applies to all TI A53
platforms as well.

See the following for further information:
https://developer.arm.com/documentation/epm048406/2100

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ic095424ce510139e060b38cfb84509d2cc573cad

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maintainers: Update maintainers for TI port

Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.

Signed-off-by: Nishanth Menon <nm@ti.com>
Cha

maintainers: Update maintainers for TI port

Andrew is no longer with TI unfortunately, so stepping up to provide
maintainer for supported TI platforms.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ia1be294631421913bcbc3d346947195cb442d437

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Merge changes from topic "zynqmp-update-pinctrl-api" into integration

* changes:
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
zynqmp: pm: Reimplement pinctrl set/get f

Merge changes from topic "zynqmp-update-pinctrl-api" into integration

* changes:
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
zynqmp: pm: Implement pinctrl request/release EEMI API
zynqmp: pm: Update return type in query functions

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Merge "PSCI: fix limit of 256 CPUs caused by cast to unsigned char" into integration

Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration

* changes:
mediatek: mt8192: add rtc power off sequence
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192:

Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration

* changes:
mediatek: mt8192: add rtc power off sequence
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Add MPU support

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Merge changes I3703868b,Ie77476db into integration

* changes:
allwinner: Add SPC security setup for H6
allwinner: Add R_PRCM security setup for H6

Merge "allwinner: Fix non-default PRELOADED_BL33_BASE" into integration

Merge "allwinner: Enable workaround for Cortex-A53 erratum 1530924" into integration

Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration

* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use

Merge changes I0c5f32e8,Id49c124c,Idcfe933d into integration

* changes:
allwinner: Use RSB for the PMIC connection on H6
allwinner: Return the PMIC to I2C mode after use
allwinner: Always use a 3MHz RSB bus clock

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PSCI: fix limit of 256 CPUs caused by cast to unsigned char

In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As

PSCI: fix limit of 256 CPUs caused by cast to unsigned char

In psci_setup.c psci_init_pwr_domain_node() takes an unsigned
char as node_idx which limits it to initialising only the first
256 CPUs. As the calling function does not check for a limit of
256 I think this is a bug so change the unsigned char to
uint16_t and change the cast from the calling site in
populate_power_domain_tree().

Also update the non_cpu_pwr_domain_node structure lock_index
to uint16_t and update the function signature for psci_lock_init()
appropriately.

Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add
a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot
exceed the index value.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45

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Merge changes from topic "tc0_optee_sp" into integration

* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_C

Merge changes from topic "tc0_optee_sp" into integration

* changes:
fdts: tc0: Add reserved-memory node for OP-TEE
plat: tc0: OP-TEE as S-EL1 SP with SPMC at S-EL2
docs: arm: Add OPTEE_SP_FW_CONFIG
plat: tc0: enable opteed support
plat: arm: Increase SP max size

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drivers: renesas: rcar: eMMC driver code clean up

Fix checkpatch warnings and MISRA defects.

There are no functional changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad

drivers: renesas: rcar: eMMC driver code clean up

Fix checkpatch warnings and MISRA defects.

There are no functional changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I349a8eaa7bd6182746ba5104ee9fe48a709c24fd

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