fix(xilinx): resolve misra rule 8.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.6:
- An identifier with external linkage shall have exactly one external
definit

fix(xilinx): resolve misra rule 8.6 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.6:
- An identifier with external linkage shall have exactly one external
definition.
- Fix:
- Removed redundant function declarations since it is not defined.

Change-Id: If003efbfa08ee6ff4f545605ef34dfd16f33b664
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 11.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.11.3:
- A cast shall not be performed between a pointer to object type and a
poin

fix(xilinx): resolve misra rule 11.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.11.3:
- A cast shall not be performed between a pointer to object type and a
pointer to a different object type.
- Fix:
- Removed unnecessary cast of pointers.

Change-Id: Iba5dbec0784dcaa86e3a00bd213cbc2711d12029
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 2.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.2:
- There shall be no dead code.
- Fix:
- Moved code to macro protected section.

fix(xilinx): resolve misra rule 2.2 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.2.2:
- There shall be no dead code.
- Fix:
- Moved code to macro protected section.

Change-Id: I58b340aa452b67ba765dfe33ff7eb64a4eac8624
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 15.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.15.7:
- All if...else if constructs shall be terminated with an else statement.
- Fix

fix(xilinx): resolve misra rule 15.7 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.15.7:
- All if...else if constructs shall be terminated with an else statement.
- Fix:
- Convert the final else if into an else statement to comply with
MISRA guidelines

Change-Id: I1f54d955958538529a10f146a506ce2a3474f8d7
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 8.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or function
with e

fix(xilinx): resolve misra rule 8.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or function
with external linkage is defined.
- Fix:
- Declared variable as static.

Change-Id: I44a022de3d5a62d255e2481dc1f4d1e8df2c7eb0
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 8.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.3:
- All declarations of an object or function shall use the same names
and type

fix(xilinx): resolve misra rule 8.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.3:
- All declarations of an object or function shall use the same names
and type qualifiers.
- Fix:
- Made same name parameters and type qualifiers in function declaration
and definition.

Change-Id: Idb4f986cec957102bb4ba1ef22f2e7937aaeb54d
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 14.4 violation

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.14.4:
- The controlling expression of an if statement and the controlling
expressi

fix(xilinx): resolve misra rule 14.4 violation

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.14.4:
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.
- Fix:
- Converted controlling expression of if statement into essential
Boolean type.

Change-Id: I2642ff4d6446bc0719d27cd95b1ad35c36f40211
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
ar

fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
- Fix:
- Made data type same for both the operands.

Change-Id: I0cea19477f3c10265d95ea1d5d2ea151dbf174bb
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(xilinx): resolve misra rule 10.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narr

fix(xilinx): resolve misra rule 10.3 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category.
- Fix:
- Explicitly type casted to narrower essential type or of a different
essential type category.

Change-Id: Ia4258d2d0655f7847f832804a13d182ac0a2a29b
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

show more ...

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementatio

fix(versal-net): enable PSCI reset2 interface

Enable the PSCI reset2 interface for Versal NET. Since warm/soft reset
functionality is not supported in the Versal NET system, the reset2
implementation is aligned with the existing PSCI reset interface.

This implementation allows the external users to define
platform-specific actions for warm/soft reset within the reset2
handler if needed.

Change-Id: Ibb937e4c0994a29b45b9b19f8addad56fe7e7e23
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

show more ...

fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa47

fix(zynqmp): fix syscnt frequency for QEMU

QEMU uses a 62.5MHz clock frequency for the ARM generic timers.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: Ib846e17feb3cd44878a62add320fa4795fd5c69e

show more ...

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by:

fix(versal): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I3d07808821da3bdd46be819ad829cb284f9d53d3
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-

fix(versal-net): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: I153d26bd92ea26efcd7f236e2f1d89c3e5442ba4
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by:

fix(zynqmp): handle invalid entry point in cpu hotplug scenario

Invalid addresses are from 2G-4G and also address where TF-A is.

Change-Id: Iedb817a2f9667b7d0b9a3ac03891a5b93295bf87
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

Merge "feat(zynqmp): add pin group for lower qspi interface" into integration

fix(xilinx): avoid unexpected variable update

The commit 50ab13577fd5 ("fix(xilinx): typecast expression to match
data type") introduced a change where the isenabler1 variable is
modified within the

fix(xilinx): avoid unexpected variable update

The commit 50ab13577fd5 ("fix(xilinx): typecast expression to match
data type") introduced a change where the isenabler1 variable is
modified within the loop iterating over GICD_ISENABLER registers.
Instead of computing the offset from the base address for each
register, the offset is accumulated incorrectly, leading to an
incorrect register read.

As a result, some GIC enablers, including the RTC device were missed,
so pm_set_wakeup_source was not called for them and the
suspend-resume use case was failed because of that.

Fix the logic to ensure the correct offset calculation for each
iteration, preserving the intended behavior.

Fixes: 50ab13577fd5 fix(xilinx): typecast expression to match data type
Change-Id: Iec5bafcbde21078545a37259b2cf0353585ef1fa
Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

show more ...

feat(zynqmp): add pin group for lower qspi interface

ZynqMP provides two QSPI interfaces on MIO[0..12],
but the existing pin group definitions only allow
all or none of the pins to be configured for

feat(zynqmp): add pin group for lower qspi interface

ZynqMP provides two QSPI interfaces on MIO[0..12],
but the existing pin group definitions only allow
all or none of the pins to be configured for QSPI.

This is an issue on platforms that use only the lower
QSPI interface and require the remaining pins to be
configured for other purposes such as general I/O.

Add pin groups to support QSPI on MIO[0..4] with SS
(slave select) on MIO5, freeing up MIO[7..12] for
other uses.

The new pin groups can be accessed from Linux as
'qspi0_1_grp' and 'qspi_ss_1_grp'.

Change-Id: Ibdb3f13d4ba9194a3be8ce5e63478d9066d087ac
Signed-off-by: Carsten Hansen <Carsten.Hansen@bksv.com>
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

show more ...

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM func

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

show more ...

fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic d

fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic due to the absence of a console type.
Added fallback option and check for zero base address.

Change-Id: I5f5e0222685ba015ab7db2ecbd46d906f5ab9116
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
o

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.

Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapal

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Si

chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

show more ...

fix(zynqmp): fix length of clock name

The CLK_NAME_LEN variable is set to 15 but with more
hardening we get the following error for the
pss_alt_ref_clk name so bump the length slightly
to take all t

fix(zynqmp): fix length of clock name

The CLK_NAME_LEN variable is set to 15 but with more
hardening we get the following error for the
pss_alt_ref_clk name so bump the length slightly
to take all the requirements into account.

plat/xilinx/zynqmp/pm_service/pm_api_clock.c:2248:25: error: initializer-string for array of ‘char’ is too long [-Werror=unterminated-string-initialization]
2248 | .name = "pss_alt_ref_clk",
| ^~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors

Fixes: caae497df ("zynqmp: pm: Add clock control EEMI API and ioctl functions")
Change-Id: I399271dd257c6e40a2d319c47f2588a958a5491b
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>

show more ...

Merge "fix(versal-net): remove_redundant_lock_defs" into integration