xilinx: versal: Add query data API

Add PM_QUERY_DATA API to pass query data
EEMI call from Linux to PLM .

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@x

xilinx: versal: Add query data API

Add PM_QUERY_DATA API to pass query data
EEMI call from Linux to PLM .

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I18735b72ab9cb62fb6cbc7582e77de6cb57f99b0

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xilinx: versal: Add request wakeup API

Implement request wakeup API for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I40a

xilinx: versal: Add request wakeup API

Implement request wakeup API for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I40a2a4ea85bf05623ac8a17ef4a6fa329babd27e

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xilinx: versal: Add PM_INIT_FINALIZE API for versal

PM_INIT_FINALIZE is not required for versal. To use Linux
Zynqmp PM driver for versal, handle PM_INIT_FINALIZE API
in ATF for versal by always ret

xilinx: versal: Add PM_INIT_FINALIZE API for versal

PM_INIT_FINALIZE is not required for versal. To use Linux
Zynqmp PM driver for versal, handle PM_INIT_FINALIZE API
in ATF for versal by always returning SUCCESS.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I6fe5445d78e713d70282ac8931ff8b17c96b2a14

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xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API

PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware
driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API
for versal.

xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API

PM_GET_TRUSTZONE_VERSION API is required to use zynqmp-firmware
driver for versal. Add support of PM_GET_TRUSTZONE_VERSION API
for versal.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie1c859890096024cc8be67386e3fd0f5f8a4385f

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xilinx: versal: enable ipi mailbox service

Enable IPI mailbox service on versal platform.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Chang

xilinx: versal: enable ipi mailbox service

Enable IPI mailbox service on versal platform.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Idfba3bcd7e7b868133da0bc1d03c96db2d0bb1b7

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xilinx: move ipi mailbox svc to xilinx common

As IPI mailbox service is common to both ZynqMP and Versal,
move it to xilinx/common.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by

xilinx: move ipi mailbox svc to xilinx common

As IPI mailbox service is common to both ZynqMP and Versal,
move it to xilinx/common.

Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I1a7008ccf7930829621147922d2c6d8d46df5502

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plat: xilinx: versal: Implement PM IOCTL API

Add PM IOCTL EEMI.

Below PLL related IOCTLs are not available in versal PLM.
* IOCTL_SET_PLL_FRAC_MODE
* IOCTL_GET_PLL_FRAC_MODE
* IOCTL_SET_PLL_FRAC

plat: xilinx: versal: Implement PM IOCTL API

Add PM IOCTL EEMI.

Below PLL related IOCTLs are not available in versal PLM.
* IOCTL_SET_PLL_FRAC_MODE
* IOCTL_GET_PLL_FRAC_MODE
* IOCTL_SET_PLL_FRAC_DATA
* IOCTL_SET_PLL_FRAC_DATA

PLM has new EEMI APIs for PLL related operations.
Call them instead of passing IOCTL API to PLM.
For other IOCTL, ATF just pass through IOCTL
request to PLM (Platform Loader and Manager).

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I96f8da46a4d3965c9291b7b2da96056408137839

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xilinx: versal: Implement power down/restart related EEMI API

Add power down/restart related below API
- Force power down
- System shutdown

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Sig

xilinx: versal: Implement power down/restart related EEMI API

Add power down/restart related below API
- Force power down
- System shutdown

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Icd4a922923b1fd50eca1f5361f1e604aedcdb529

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xilinx: versal: Add SMC handler for EEMI API

Add SMC handler for EEMI API calls coming from EL1/EL2.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx

xilinx: versal: Add SMC handler for EEMI API

Add SMC handler for EEMI API calls coming from EL1/EL2.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If0ef2a1f2cfc2747be6b91828371bcbec56b1e15

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xilinx: versal: Implement PLL related PM APIs

Implement below PLL related APIs:
- Set PLL parameter
- Get PLL parameter
- Set PLL mode
- Get PLL mode

Signed-off-by: Tejas Patel <tejas.patel@xilinx.

xilinx: versal: Implement PLL related PM APIs

Implement below PLL related APIs:
- Set PLL parameter
- Get PLL parameter
- Set PLL mode
- Get PLL mode

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I37749d05cdb73641d32da120d319cf36df97c73f

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xilinx: versal: Implement clock related PM APIs

Implement below clock related APIs:
- Clock enable
- Clock disable
- Clock get status
- Clock set divider
- Clock get divider
- Clock set

xilinx: versal: Implement clock related PM APIs

Implement below clock related APIs:
- Clock enable
- Clock disable
- Clock get status
- Clock set divider
- Clock get divider
- Clock set parent
- Clock get parent

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ibb3606e88ac6796d9d759226908b2c2997c5fea0

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xilinx: versal: Implement pin control related PM APIs

Implement below pin control related APIs:
- Request pin
- Release pin
- Set pin function
- Get pin function
- Set pin parameter value

xilinx: versal: Implement pin control related PM APIs

Implement below pin control related APIs:
- Request pin
- Release pin
- Set pin function
- Get pin function
- Set pin parameter value
- Get pin parameter value

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ib805cc8c936b63206d44bf1f7bebd0f03f7b3c01

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xilinx: versal: Implement reset related PM APIs

Implement below reset related APIs:
- Reset assert
- Get reset status

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Sh

xilinx: versal: Implement reset related PM APIs

Implement below reset related APIs:
- Reset assert
- Get reset status

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id42c9d3950a0d69125cb0eab79b75e5d22674f14

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xilinx: versal: Implement device related PM APIs

Implement below device related PM APIs:
- Request device
- Release device
- Set requirement
- Get device status

Signed-off-by: Tejas Patel <

xilinx: versal: Implement device related PM APIs

Implement below device related PM APIs:
- Request device
- Release device
- Set requirement
- Get device status

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I9d84b9ee1be3ee6c5f27a4d6dc324113fc1acb68

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xilinx: versal: Add support for suspend related APIs

Add support for below suspend related APIs.
- self_suspend
- abort_suspend
- request_suspend

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>

xilinx: versal: Add support for suspend related APIs

Add support for below suspend related APIs.
- self_suspend
- abort_suspend
- request_suspend

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: If568e0cd33b64754fe66f66fc0cdd0ec62c1b32e

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xilinx: versal: Add get_api_version support

Add support for EEMI API get_api_verion.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id:

xilinx: versal: Add get_api_version support

Add support for EEMI API get_api_verion.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic1ef90a194ae6164994a7fc5d8ff0b7b192636fe

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xilinx: Add support to send PM API to PMC using IPI for versal

Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by

xilinx: Add support to send PM API to PMC using IPI for versal

Port ZynqMP PM services for versal to send PM APIs to PMC
using IPI.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Wendy Liang <wendy.liang@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I27a52faf27f1a2919213498276a6885a177cb6da

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plat: xilinx: versal: Move versal_def.h to include directory

Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def

plat: xilinx: versal: Move versal_def.h to include directory

Move versal_def.h to platform specific include directory.
Also, update source file to include header file from updated
path of versal_def.h

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I313592a17552843b9cc7048f31bcaaefa40ffd91

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plat: xilinx: versal: Move versal_private.h to include directory

Move versal_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So,

plat: xilinx: versal: Move versal_private.h to include directory

Move versal_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I65eefbea7722ffa2760b992491c00eebef5bcef4

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plat: xilinx: zynqmp: Use GIC framework for warm restart

- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC

plat: xilinx: zynqmp: Use GIC framework for warm restart

- Flag GICV2_G0_FOR_EL3 needs to be set for group interrupts
to be targeted to EL3.
- Raise SGI interrupts for individual CPU cores as GIC API
uses CPU num as parameter, not CPU mask.
- Flag WARMBOOT_ENABLE_DCACHE_EARLY needs to be set to enable
CPU interface mask work properly for all CPU cores which is
required when generating SGI.
- Call plat_ic_end_of_interrupt() from ttc_fiq_handler() to clear
GIC interrupt to avoid same interrupt again.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I71d4935b8d4688a3729c62753ca8a1a77cd92ae7

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plat: xilinx: zynqmp: Add checksum support for IPI data

This patch adds support for CRC checksum for IPI data when the
macro ZYNQMP_IPI_CRC_CHECK is defined.

Signed-off-by: Venkatesh Yadav Abbarapu

plat: xilinx: zynqmp: Add checksum support for IPI data

This patch adds support for CRC checksum for IPI data when the
macro ZYNQMP_IPI_CRC_CHECK is defined.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic981f162666b3c1fffeb1b9fef3ee7714ecd889d

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zynqmp: pm_service: Add support to query max divisor

Add new QID to get maximum supported divisor by clock.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel

zynqmp: pm_service: Add support to query max divisor

Add new QID to get maximum supported divisor by clock.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35fc92457e522f3f0614d983c21e55c2b0b8e80a

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zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value t

zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

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zynqmp: pm: clock: Move custom flags to typeflags

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Va

zynqmp: pm: clock: Move custom flags to typeflags

Linux expects custom flags in type flags. So move
custom flags to type flags instead of providing
them to clock core flags.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78

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zynqmp: pm: clock: Add support for custom type flags

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off

zynqmp: pm: clock: Add support for custom type flags

Add support to add extra custom type flags and provide
to caller in topology query.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Id9cc065dbadfed2291dd4f62674d7838da4cdf40

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