| 5897e135 | 26-Aug-2022 |
Tanmay Shah <tanmay.shah@xilinx.com> |
fix(versal): add SGI register call version check
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes versi
fix(versal): add SGI register call version check
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0
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|
| 4264bd33 | 23-Aug-2022 |
Akshay Belsare <Akshay.Belsare@amd.com> |
fix(zynqmp): fix for incorrect afi write mask value
Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
upda
fix(zynqmp): fix for incorrect afi write mask value
Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
updated the mask value handling logic.
Signed-off-by: Nava kishore Manne <nava.kishore.manne@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Acked-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Change-Id: I8443c369a84339018310cfb6cd498d21474da3e4
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|
| 000e25bf | 07-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal): use only one space for indentation" into integration |
| dee58859 | 04-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): use only one space for indentation
Trivial patch to remove additional space.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifa33dee81243c0b21ca0f13b8e4d575646818162 |
| 72583f92 | 29-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): fix code indentation issues
Next line should be aligned with the previous code.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I20d82ba5fa70fa252341b62e57fac265241f3391 |
| 80806aa1 | 27-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): fix macro coding style issues
Use only one space between #define and macro name.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ieb9bdd5bcfa56bd265df72692a09c7340fe132cb |
| 342a65fb | 01-Aug-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): protect eFuses from non-secure access" into integration |
| 19f92c4c | 31-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(versal): resolve misra 10.1 warnings
MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venk
fix(versal): resolve misra 10.1 warnings
MISRA Violation: MISRA-C: 2012 R.10.1
-The operand to the operator does not have an essentially
unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4873a620086dfd6f636fe730165a9d13a29e9652
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|
| f7c48d9e | 31-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by:
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ieff90b5311a3bde8a2cb302ca81c23eeee6d235a
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|
| d0b7286e | 29-Apr-2022 |
Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> |
feat(zynqmp): protect eFuses from non-secure access
When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.
This enables eFu
feat(zynqmp): protect eFuses from non-secure access
When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.
This enables eFuses to be reserved and protected only for security use
cases for example in OP-TEE.
Change-Id: I866905e35ce488f50f5f6e1b4667b08a9fa2386d
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
show more ...
|
| bfc514f1 | 28-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal S
fix(xilinx): miscellaneous fixes for xilinx platforms
This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9
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|
| 47f81453 | 21-Jul-2022 |
Michal Simek <michal.simek@amd.com> |
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also p
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.
Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
|
| b86e1aad | 20-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(versal): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <
feat(versal): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
-The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9cde2f1ebceaad8a41c69489ef1d2e6f21f04ed1
show more ...
|
| 205c7ad4 | 12-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(versal): get the handoff params using IPI
Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the is
feat(versal): get the handoff params using IPI
Use the IPI command GET_HANDOFF_PARAM to get the TF-A handoff
params, rather than using the PLM's PPU RAM area. With this
approach this resolves the issue when XPPU is enabled.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6828c391ad696d2d36e994684aa21b023711ba2d
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|
| 237a7de1 | 12-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
refactor(xilinx): move the atf handoff structure
Move the ATF handoff structure from the plat_startup.c to the
header file plat_startup.h, as these can be used by the platform code.
Signed-off-by:
refactor(xilinx): move the atf handoff structure
Move the ATF handoff structure from the plat_startup.c to the
header file plat_startup.h, as these can be used by the platform code.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ifb425d444eb65fe8648952d2ff64d4e92c2b340a
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|
| 7e5f0abf | 12-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
refactor(versal): move payload and module ID macros
Move the payload and module ID macros from the pm_api_sys.c file and
add it in the header file, as these macros can be used other than PM.
Signe
refactor(versal): move payload and module ID macros
Move the payload and module ID macros from the pm_api_sys.c file and
add it in the header file, as these macros can be used other than PM.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Change-Id: I678444b79ac3799a82bd93915e4639b3babf5fb9
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|
| bfd7c881 | 04-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The op
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I97bbc056f4fee167742429e144144ba793bf77b3
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|
| 57ab7497 | 29-Jun-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_zynqmp_misra_fix1" into integration
* changes:
fix(zynqmp): resolve the misra 8.6 warnings
fix(zynqmp): resolve the misra 4.6 warnings |
| 9316149e | 24-Jun-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(zynqmp): move bl31 with DEBUG=1 back to OCM" into integration |
| 40366cb6 | 24-Jun-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xlnx_versal_misra_fix" into integration
* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 w
Merge changes from topic "xlnx_versal_misra_fix" into integration
* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 warnings
fix(versal): resolve the misra 4.6 warnings
show more ...
|
| 389594df | 15-Jun-2022 |
Michal Simek <michal.simek@xilinx.com> |
fix(zynqmp): move bl31 with DEBUG=1 back to OCM
By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should b
fix(zynqmp): move bl31 with DEBUG=1 back to OCM
By default placing bl31 to addrexx 0x1000 is not good. Because this
location is used by U-Boot SPL. That's why move TF-A back to OCM where it
should be placed. BL31_BASE address exactly matches which requested address
for U-BOOT SPL boot flow.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I608c1b88baffec538c6ae528f057820e34971c4c
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|
| 86869f99 | 17-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): add support for xck24 silicon
Add support for new xck24 device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilin
feat(zynqmp): add support for xck24 silicon
Add support for new xck24 device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I913a34d5a48ea665aaa4348f573fc59566dd5a9b
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|
| 7b1a6a08 | 19-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): resolve the misra 8.6 warnings
MISRA Violation: MISRA-C:2012 R.8.6
- Function is declared but never defined.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Cha
fix(zynqmp): resolve the misra 8.6 warnings
MISRA Violation: MISRA-C:2012 R.8.6
- Function is declared but never defined.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0df53ef4b2c91fa8ec3bf3e5491bf37dd7400685
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|
| ffa91031 | 19-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by:
fix(zynqmp): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9fb686e7aa2b85af6dfcb7bb5f87eddf469fb85c
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|
| 5e529e32 | 03-Jun-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/zynqmp): fix coverity scan warnings" into integration |